MSM5299A
Semiconductor
1/11
GENERAL DESCRIPTION
The MSM5299A is a dot matrix LCD segment driver LSI which is fabricated using CMOS low
power metal gate technology. This LSI consists of an 80-bit bidirectional shift register, 80-bit
latch, 80-bit level shifter and 80-bit 4-level driver.
It receives the display data, which is transferred in 4-bit parallel from a microcomputer or LCD
controller LSI such as MSM6255, then outputs the LCD driving waveform to the LCD.
FEATURES
Supply voltage
: 4.5 to 5.5V
LCD driving voltage
: 8 to 28V
Applicable LCD duty
: 1/64 to 1/256
LCD Output
: 80
The 4-bit parallel data processing has improved the transfer speed to 1/4 that of the
conventional serial transfer, thereby achieving low power consumption
Can be interfaced with the LCD controller LSI MSM6255
Applicable common diriver : MSM5298A (68 outputs)
Package options:
100-pin plastic QFP
(QFP100-P-1420-0.65-K) (Product name : MSM5299AGS-K)
100-pin plastic QFP
(QFP100-P-1420-0.65-BK) (Product name : MSM5299AGS-BK)
Semiconductor
MSM5299A
80-DOT LCD SEGMENT DRIVER
E2B0020-27-Y2
This version: Nov. 1997
Previous version: Mar. 1996
MSM5299A
Semiconductor
2/11
O
1
O
2
O
79
O
80
V
1
V
3
V
4
V
EE
DF
DISP OFF
LOAD
D
0
D
1
D
2
D
3
CP
EL
Control
Circuit
4 x 20-Bit Bidirectional Shift Register
80-Bit Latch (Edge trigger D-F/F)
80-Bit Level Shifter
SHIFT CP
SHL
V
DD
V
SS
ER
V
EE
V
DD
80-Bit 4-Level Driver
V
SS
V
DD
BLOCK DIAGRAM
MSM5299A
Semiconductor
3/11
NC : No connection
100-Pin Plastic QFP
Note: The abbreviated part number "M5299A" is imprinted on the package surface.
O
65
O
66
O
67
O
68
O
69
O
51
O
52
O
53
O
54
O
55
O
56
O
57
O
58
O
59
O
60
O
61
O
62
O
63
O
64
O
70
O
71
O
72
O
73
O
74
O
37
O
36
O
35
D2
D1
EL
O
43
O
48
O
49
O
50
NC
O
28
O
26
O
25
O
24
O
23
O
22
O
21
O
20
O
19
O
18
O
17
ER
NC
V
EE
V
4
V
3
V
1
O
27
O
42
O
44
O
45
O
47
O
46
O
41
O
40
O
39
O
38
DF
DISPOFF
V
DD
SHL
V
SS
D3
O
16
O
15
O
14
O
13
O
12
O
30
O
29
O
11
O
10
O
9
O
8
O
7
44
45
46
87
86
85
15
16
17
18
19
4
3
2
1
5
6
7
8
9
10
11
12
13
14
31
32
33
34
35
36
37
38
39
40
41
42
43
77
78
79
80
76
75
74
73
72
71
70
69
68
67
100
99
98
97
96
95
94
93
92
91
90
89
88
66
65
64
63
62
20
21
22
23
24
61
60
59
58
57
25
56
26
27
28
29
30
55
54
53
52
51
48
49
50
83
82
81
47
84
O
33
O
32
O
31
O
34
O
6
O
5
O
4
O
3
O
2
O
1
O
75
O
76
O
77
O
78
O
79
O
80
LOAD
D0
CP
NC
PIN CONFIGURATION (TOP VIEW)
MSM5299A
Semiconductor
4/11
ABSOLUTE MAXIMUM RATINGS
*1 V
DD
V
1
>V
3
>V
4
>V
EE
RECOMMENDED OPERATING CONDITIONS
Storage Temperature
55 to +150
T
STG
Ta = 25C, V
DD
V
EE
Ta = 25C
--
C
Parameter
Symbol
Condition
Rating
Unit
Supply Voltage (1)
Supply Voltage (2)
Input Voltage
0.3 to +6
0 to 30
0.3 to V
DD
+0.3
V
DD
V
LCD
*1
V
I
Ta = 25C
V
V
V
(V
SS
=0V)
*1 V
DD
V
1
>V
3
>V
4
>V
EE
Parameter
Symbol
Condition
Range
Unit
Supply Voltage (1)
Supply Voltage (2)
Operating Temperature
4.5 to 5.5
8 to 28
20 to +85
V
DD
V
LCD
T
op
--
V
V
C
V
DD
V
EE
--
*1
(V
SS
=0V)
MSM5299A
Semiconductor
5/11
ELECTRICAL CHARACTERISTICS
DC Characteristics
13
15
2
15
*1 Applicable to LOAD, CP, D
0
- D
3
, EL, ER, SHL, DF, DISP OFF
*2 Applicable to EL, ER.
*3 V
N
= V
DD
to V
EE,
V
4
= (V
DD
V
EE
), V
3
= (V
DD
V
EE
), V
1
= V
DD
*4 Applicable to O
1
to O
80
.
*5 Display data 1010 ......f
DF
= 40 Hz, Current from V
DD
to V
SS
when the display data is not
processing.
*6 Display data 1010 ......f
DF
= 40 Hz, Current from V
DD
to V
SS
when the display data is
processing.
*7 Display data 1010 ......f
DF
= 40 Hz, Current on V
1
, V
3
and V
4
.
(V
DD
= 5V 10%, Ta = 20 to +85C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
"H" Input Voltage
V
IH
0.8V
DD
--
V
DD
V
*1
--
"L" Input Voltage
V
IL
V
SS
--
0.2V
DD
V
*1
--
"H" Input Current
V
IH
--
--
1
mA
*1
V
IH
= V
DD
, V
DD
= 5.5V
V
IL
--
--
1
mA
*1
V
IL
= 0V, V
DD
= 5.5V
"H" Input Current
"H" Output Voltage
V
OH
V
DD
0.4
--
--
V
*2
I
O
=
0.2mA, V
DD
= 4.5V
"L" Output Voltage
V
OL
--
--
0.4
V
*2
I
O
=
0.2mA, V
DD
= 4.5V
ON Resistance
R
ON
--
2
4
kW
*4
V
DD
V
EE =
23V
V
N
V
O =
0.25V, V
DD
= 4.5V
*3
Stand-by Current
I
DDSBY
--
--
200
mA
f
CP
= 1MHz, V
DD
= 5.5V
V
DD
V
EE =
26V, No load
*5
Supply Current (1)
I
DD1
--
--
3
mA
f
CP
=1MHz, V
DD
= 5.5V
V
DD
V
EE =
26V, No load
*6
Supply Current (2)
I
V
--
--
100
mA
f
CP
= 1MHz, V
DD
= 5.5V
V
DD
V
EE =
26V, No load
*7
Input Capacitance
C
I
--
5
--
pF
f = 1MHz
MSM5299A
Semiconductor
6/11
Switching Characteristics
Clock Frequency
Clock, Load Pulse Width
Clock Pulse Rise/Fall Time
Data Set-up Time
Data Hold Time
Load Set-up Time
Load Clock Time
Propagation Delay Time
ER, EL Set-up Time
f
CP
t
W
t
r
, t
f
t
DSU
t
DHD
t
LSU
t
LC
t
PHL
t
ESU
DUTY=50%
--
100
--
50
80
90
200
--
70
--
--
--
--
--
--
--
--
--
3.4
--
50
--
--
--
--
--
224
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
t
f
t
W
t
W
t
W
t
r
0.8V
DD
0.8V
DD
0.2V
DD
0.2V
DD
0.8V
DD
0.8V
DD
t
DSU
t
DHD
0.8V
DD
0.8V
DD
0.2V
DD
0.2V
DD
t
LSU
0.8V
DD
0.8V
DD
t
LC
0.2V
DD
0.2V
DD
t
r
t
f
t
W
CP
D
0
- D
3
LOAD
CP
LOAD
ER, EL (Output)
EL, ER (Input)
1
2
19
20
0.8V
DD
0.2V
DD
0.2V
DD
t
ESU
t
PHL
0.2V
DD
(V
DD
= 5V 10%, Ta = 20 to +75C, C
L
= 15pF)
--
--
--
--
--
--
--
--
MSM5299A
Semiconductor
7/11
FUNCTIONAL DESCRIPTION
Pin Functional Description
ER, EL
When single MSM5299A is used, ER (EL) should be set at "L" level.
When a cascade connection is required, set the ER (EL) pin of the first MSM5299A at "L" level
and connect the EL (ER) pin of the first MSM5299A to the ER (EL) pin of the second MSM5299A,
then connect the EL (ER) pin of the second MSM5299A to the ER (EL) pin of the third MSM5299A.
CP
Clock pulse input pin for the 4-bit parallel shift register. The data is shifted to 4 20-bit shift
register at the falling edge of the clock pulse. The clock pulse is activated when the ENABLE
F/F is set and is deactivated when the ENABLE F/F is not set.
SHL
Input pin to switch the input or output of pins ER and EL, and the shift direction of the 4-bit
parallel bidirectional shift register.
The shift direction of the 4-bit parallel data, the correspondence of the data D
0
to D
3
to the
driver outputs O
1
to O
80
, and the input and output state of pins ER and EL are shown in the
table below.
SHL
L
H
Input
Output
Output
Input
ER
EL
Shift direction
D
0
D
1
D
2
D
3
O
1
O
2
O
3
O
4
D
0
D
1
D
2
D
3
O
5
O
6
O
7
O
8
O
77
O
78
O
79
O
80
O
80
O
79
O
78
O
77
O
76
O
75
O
74
O
73
O
4
O
3
O
2
O
1
end data
start data
Pin
Input/Output
SHL
Description
Input pin to ENABLE F/F of MSM5299A.
Output pin of ENABLE F/F. EL is connected to next MSM5299A's
ER when MSM5299As are connected in series (cascade
connection).
Input pin to ENABLE F/F of MSM5299A.
Output pin of ENABLE F/F. ER is connected to next MSM5299A's
EL when MSM5299As are connected in series (cascade
connection).
L
H
Input
Output
Input
Output
ER
EL
EL
ER
MSM5299A
Semiconductor
8/11
D
0
, D
1
, D
2
, D
3
Display data input pins for 4 20-bit shift register. The display data is clocked into the shift
register at the falling edge of the clock pulse. The combinations of D
0
to D
3
level, DF signal
level, display data output level and the display on the LCD panel are described on the table
below.
LOAD
The signal for latching the shift register contents is input to this pin. The display data stored
in the shift register is latched at the falling edge of the load pulse.
DF
Synchronous signal input pin for alternate signal for LCD driving.
V
DD
, V
SS
Supply voltage pins, V
DD
should be 4.5 to 5.5V. V
SS
is a ground pin (V
SS
= 0V)
V
1
, V
3
, V
4
, V
EE
Bias supply voltage pin to drive the LCD. Use an external bias voltage supply for driving the
LCD.
L
H
L
H
L
L
H
H
OFF
ON
OFF
ON
D
0
to D
3
DF
Display data output level
Display on the LCD
Nonselect level (V
3
)
Select level (V
1
)
Nonselect level (V
4
)
Select level (V
EE
)
MSM5299A
Semiconductor
9/11
Truth Table
X : Don't care
O
1
- O
80
Display data output pins, which correspond to the respective latch contents. One of V
1
, V
3
,
V
4
and V
EE
is selected as a display driving voltage source according to the combination of the
latched data level and DF signal. Refer to the Truth Table.
The outputs O
1
to O
80
are connected to the segment side of the LCD panel.
DISP OFF
Input pin to control outputs of O
1
to O
80
. V
1
level is output from O
1
to O
80
pins during "L"
level input. Refer to the Truth Table.
DF
Latched data
DISP OFF
LCD driver output (O
1
- O
80
)
L
L
H
H
X
L
H
L
H
X
H
H
H
H
L
V
3
V
1
V
4
V
EE
V
1
NOTES ON USE
Note the following when turning power on and off:
The LCD drivers of this IC require a high voltage. For this reason, if a high voltage is applied to
the LCD drivers with the logic power supply floating, excess current flows. This may damage
the IC. Be sure to carry out the following power-on and power-off sequences:
When turning power on:
First V
DD
ON, next V
EE
, V
4
, V
3
, V
1
ON. Or both ON at the same time.
When turning power off:
First V
EE
, V
4
, V
3
, V
1
OFF, next V
DD
OFF. Or both OFF at the same time.
MSM5299A
Semiconductor
10/11
(Unit : mm)
PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
QFP100-P-1420-0.65-K
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.29 TYP.
Mirror finish
MSM5299A
Semiconductor
11/11
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
(Unit : mm)
QFP100-P-1420-0.65-BK
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.29 TYP.
Mirror finish
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