¡ Semiconductor

MSM548263

1/40

¡ Semiconductor

MSM548263

262,144-Word

¥ 8-Bit Multiport DRAM

DESCRIPTION

The MSM548263 is a 2-Mbit CMOS multiport DRAM composed of a 262,144-word by 8-bit
dynamic RAM, and a 512-word by 8-bit SAM. Its RAM and SAM operate independently and
asynchronously.

It supports three types of operations: random access to RAM port, high speed serial access to
SAM port, and bidirectional transfer of data between any selected row in the RAM port and the
SAM port. In addition to the conventional multiport DRAM operating modes, the MSM548263
features block write, flash write functions and extended page mode on the RAM port and a split
data transfer capability, programmable stops on the SAM port. The SAM port requires no refresh
operation because it uses static CMOS flip-flops.

FEATURES

· Single power supply: 5 V

10%

· Full TTL compatibility
· Multiport organization

RAM : 256K word ¥ 8 bits
SAM : 512 word ¥ 8 bits

· Extended page mode
· Write per bit
· Persistent write per bit
· Masked flash write
· Masked block write
· Package options:

40-pin 400 mil plastic SOJ

(SOJ40-P-400-1.27)

(Product : MSM548263-xxJS)

44/40-pin 400 mil plastic TSOP (Type II)(TSOPII44/40-P-400-0.80-K)(Product : MSM548263-xxTS-K)

xx indicates speed rank.

PRODUCT FAMILY

· RAS only refresh
· CAS before RAS refresh
· Hidden refresh
· Serial read/write
· 512 tap location
· Programmable stops
· Bidirectional data transfer
· Split transfer
· Masked write transfer
· Refresh: 512 cycles/8 ms

Access Time

Cycle Time

Power Dissipation

RAM

Operating

Standby

SAM

60 ns

120 ns

140 mA

8 mA

17 ns

22 ns

70 ns

140 ns

130 mA

8 mA

17 ns

22 ns

80 ns

150 ns

120 mA

8 mA

20 ns

25 ns

Family

MSM548263-60

MSM548263-70

MSM548263-80

E2L0017-17-Y1

This version: Jan. 1998

Previous version: Dec. 1996

¡ Semiconductor

MSM548263

2/40

PIN CONFIGURATION (TOP VIEW)

Pin Name

Function

A0 - A8

Address Input

RAS

Row Address Strobe

CAS

Column Address Strobe

TRG

Transfer/Output Enable

Write Enable

Pin Name

Function

Serial Clock

SAM Port Enable

DSF

Special Function Input

Power Supply (5 V)

No Connection

DQ1 - DQ8

RAM Inputs/Outputs

SDQ1 - SDQ8

SAM Inputs/Outputs

QSF

Special Function Output

Ground (0 V)

40-Pin Plastic SOJ

44/40-Pin Plastic TSOP (

II)

(K Type)

SDQ1

SDQ2

SDQ3

SDQ4

TRG

DQ1

DQ2

DQ3

SDQ7

SDQ6

SDQ5

DQ5

DSF

NC
CAS

QSF

DQ8

DQ7

DQ6

DQ4

RAS

SDQ8

SDQ1

SDQ2

SDQ3

SDQ4

TRG

DQ1

DQ2

DQ3

DQ4

RAS

44 V

23 V

43 SDQ8
42 SDQ7
41 SDQ6
40 SDQ5
39 SE
38 DQ8
37 DQ7
36 DQ6
35 DQ5

32 V

31 DSF
30 NC
29 CAS
28 QSF
27 A0
26 A1
25 A2
24 A3

Note:

The same power supply voltage must be provided to every V

pin, and the same GND

voltage level must be provided to every V

pin.

¡ Semiconductor

MSM548263

4/40

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Parameter

Symbol

Rating

Unit

Input Output Voltage

1.0 to 7.0

Output Current

Power Dissipation

Operating Temperature

opr

0 to 70

°C

Storage Temperature

stg

55 to 150

°C

Condition

Ta = 25°C

(Note: 1)

Recommended Operating Conditions

Parameter

Symbol

Unit

Power Supply Voltage

Input High Voltage

Input Low Voltage

Min.

4.5

2.4

1.0

Typ.

5.0

Max.

5.5

6.5

0.8

(Ta = 0°C to 70°C) (Note: 2)

Capacitance

Parameter

Symbol

Min.

Unit

Input Capacitance

Input/Output Capacitance

Max.

Output Capacitance

(QSF)

= 5 V ±10%, f = 1 MHz, Ta = 25°C)

Note:

This parameter is periodically sampled and is not 100% tested.

DC Characteristics 1

Parameter

Symbol

Condition

Output "H" Level Voltage

= 1 mA

Output "L" Level Voltage

= 2.1 mA

Input Leakage Current

0 £ V

£ V

All other pins not

under test = 0 V

Min.

2.4

Max.

0.4

Unit

Output Leakage Current

0 £ V

OUT

£ 5.5 V

Output Disable

¡ Semiconductor

MSM548263

5/40

DC Characteristics 2

-60

-70

-80

Unit Note

Symbol

Item (RAM)

SAM

Max. Max. Max.

3, 4

CC1

Operating Current

Standby

140

130

120

(RAS, CAS Cycling, t

= t

min.)

Active

Standby Current

3, 4

(RAS, CAS = V

)

3, 4

RAS Only Refresh Current

140

130

120

(RAS Cycling, CAS = V

, t

= t

min.)

3, 4

Page Mode Current

140

130

120

(RAS = V

, CAS Cycling, t

= t

min.)

3, 4

CAS before RAS Refresh Current

140

130

120

3, 4

(RAS Cycling, CAS before RAS, t

= t

min.)

3, 4

Data Transfer Current

140

130

120

(RAS, CAS Cycling, t

= t

min.)

3, 4

Flash Write Current

140

130

120

3, 4

(RAS, CAS Cycling, t

= t

min.)

3, 4

Block Write Current

140

130

120

3, 4

(RAS, CAS Cycling, t

= t

min.)

CC1

CC2

CC3

CC4

CC5

CC6

CC7

CC8

Standby

Active

Standby

Active

Standby

Active

Standby

Active

Standby

Active

Standby

Active

Standby

Active

= 5 V ±10%, Ta = 0°C to 70°C)

¡ Semiconductor

MSM548263

6/40

AC Characteristics (1/3)

Parameter

Symbol

Note

Unit

150

140

120

100k

PRWC

CAC

CPA

RASP

CAS

RCD

Max.

Min.

Max.

Min.

Max.

Min.

-80

-70

-60

10k

RAC

OFF

RSH

CSH

10k

RAS

RAD

ASR

RAH

ASC

CAH

RCS

RCH

RRH

WCS

WCH

WCR

RWL

CWL

8, 14

8, 15

8, 14

195

185

170

RWC

CRL

RCL

COH

RAL

CRP

Access Time from Column Address

Column Address Hold Time referenced to RAS

Column Address Set-up Time

Row Address Set-up Time

Access Time from CAS

Column Address Hold Time

CAS Pulse Width

CAS Precharge Time (Fast Page Mode)

Access Time from CAS Precharge

CAS to RAS Precharge Time

CAS Hold Time

Write Command to CAS Lead Time

Output Buffer Turn-off Delay

CAS "H" to RAS "H" Lead Time
RAS "H" to CAS "H" Lead Time

Fast Page Mode Cycle Time

Fast Page Mode Read Modify Write Cycle Time

Row Address Hold Time

RAS Pulse Width (Fast Page Mode Only)

Random Read or Write Cycle Time

RAS to CAS Delay Time

Read Command Hold Time

Read Command Set-up Time

Read Modify Write Cycle

RAS Precharge Time

Read Command Hold Time referenced to RAS

Write Command to RAS Lead Time

Access Time from RAS

RAS to Column Address Delay Time

Column Address to RAS Lead Time

RAS Pulse Width

RAS Hold Time

Transition Time (Rise and Fall)

Write Command Hold Time referenced to RAS

Write Command Set-up Time

Write Command Pulse Width

Write Command Hold Time

Data Output Hold after CAS Low

¡ Semiconductor

MSM548263

7/40

AC Characteristics (2/3)

Parameter

Symbol

Note

Unit

RWD

CWD

DZC

DZO

CSR

REF

WSR

Max.

Min.

Max.

Min.

Max.

Min.

-80

-70

-60

100

AWD

OEA

CHR

RPC

OEZ

OEH

ROH

RWH

FSC

CFH

THS

THH

TLS

TLH

TRP

RSD

ASD

CSD

TSL

10k

RTH

10k

ATH

CTH

FSR

RFH

FHR

Column Address to First SC Delay Time

Column Address to WE Delay Time

CAS Hold Time for CAS before RAS Cycle

CAS Set-up Time for CAS before RAS Cycle

CAS to WE Delay Time

Data to CAS Delay Time

Data to TRG Delay Time

DSF Set-up Time referenced to RAS

Write Per Bit Mask Data Hold Time

Write Per Bit Mask Data Set-up Time

TRG Command Hold Time

Refresh Period

DSF Hold Time referenced to RAS (1)

RAS Hold Time referenced to TRG

RAS Precharge to CAS Active Time

RAS to WE Delay Time

WE Hold Time

Access Time from TRG

RAS to First SC Delay Time (Read Transfer)

TRG to RAS Precharge Time

WE Set-up Time

Last SC to TRG Lead Time

Output Buffer Turn-off Delay from TRG

DSF Hold Time referenced to RAS (2)

DSF Hold Time referenced to CAS

TRG Low Hold Time referenced to Column Address
TRG Low Hold Time referenced to CAS

TRG

Precharge Time

DSF Set-up Time referenced to CAS

TRG High Hold Time

TRG High Set-up Time

TRG Low Hold Time

TRG Low Set-up Time

TRG Low Hold Time referenced to RAS

CAS to First SC Delay Time (Read Transfer)

DHR

Data Hold Time

Data Hold Time referenced to RAS

Data Set-up Time

¡ Semiconductor

MSM548263

8/40

AC Characteristics (3/3)

Parameter

Symbol

Note

Unit

SCC

SCP

SCA

SOH

STS

TQD

CQD

Max.

Min.

Max.

Min.

Max.

Min.

-80

-70

-60

SEA

STH

SQD

SEP

SEZ

RQD

SZE

SZS

SWS

SWH

SWIS

SWIH

SDD

SDS

SDH

Access Time from SC

SC-QSF Delay Time

SC Pulse Width (SC High Time)

SC Cycle Time

SC Precharge Time (SC Low Time)

RAS to Serial Input Delay Time

Split Transfer Hold Time

Split Transfer Set-up Time

SE Pulse Width

Access Time from SE

SE Precharge Time

Serial Write Disable Hold Time

Serial Write Disable Set-up Time

Serial Write Enable Set-up Time

Serial Input to SE Delay Time

Serial Input to First SC Delay Time

Serial Output Buffer Turn-off Delay from SE

Serial Output Hold Time from SC

Serial Write Enable Hold Time

TRG-QSF Delay Time
CAS-QSF Delay Time
RAS-QSF Delay Time

Serial Input Hold Time

Serial Input Set-up Time

TSD

SDZ

SRS

Serial Output Buffer Turn-off Delay from RAS

TRG to First SC Delay Time (Read Transfer)

Last SC to RAS Set-up Time (Serial Input)

¡ Semiconductor

MSM548263

9/40

Notes:

1. Exposure beyond the "Absolute Maximum Ratings" may cause permanent damage

to the device.

2. All voltages are referenced to V

3. These parameters depend on the cycle rate.
4. These parameters depend on output loading. Specified values are obtained with the

output open.

5. An initial pause of 200 ms is required after power up followed by any 8 RAS cycles

(TRG = "high") and any 8 SC cycles before proper device operation is achieved.
In the case of using an internal refresh counter, a minimum of 8 CAS before RAS
cycles instead of 8 RAS cycles are required.

6. AC measurements assume t

= 5 ns.

7. V

(Min.) and V

(Max.) are reference levels for measuring timing of input signals.

Also, transition times are measured between V

and V

8. RAM port outputs are measured with a load equivalent to 1 TTL load and 50 pF.

DOUT reference levels : V

= 2.0 V/0.8 V.

9. SAM port outputs are measured with a load equivalent to 1 TTL load and 30 pF.

DOUT

reference levels : V

= 2.0 V/0.8 V.

10. t

OFF

(Max.), t

OEZ

(Max.), t

SDZ

(Max.) and t

SEZ

(Max.) define the time at which the

outputs achieve the open circuit condition, and are not referenced to output voltage
levels. This parameter is sampled and not 100% tested.

11. Either t

RCH

or t

RRH

must be satisfied for a read cycle.

12. These parameters are referenced to CAS leading edge of early write cycles, and to

WE leading edge in TRG controlled write cycles and read modify write cycles.

13. t

WCS

, t

RWD

, t

CWD

and t

AWD

are not restrictive operating parameters.

They are included in the data sheet as electrical characteristics only.
If t

WCS

(Min.), the cycle is an early write cycle, and the data out pin will

remain open circuit throughout the entire cycle; If t

RWD

(Min.), t

CWD

(Min.) and t

AWD

(Min.), the cycle is a read modify write cycle, and the data

out will contain data read from the selected cell; If neither of the above sets of
conditions are satisfied, the condition of the data out is indeterminate.

14. Operation within the t

RCD

(Max.) limit ensures that t

RAC

(Max.) can be met.

RCD

(Max.) is specified as a reference point only: If t

RCD

is greater than the specified

RCD

(Max.) limit, then access time is controlled by t

CAC

15. Operation within the t

RAD

(Max.) limit ensures that t

RAC

(Max.) can be met. t

RAD

(Max.) is specified as a reference point only: If t

RAD

is greater than the specified t

RAD

(Max.) limit, then access time is controlled by t

16. Input levels at the AC testing are 3.0 V/0 V.
17. Address (A0 - A8) may be changed two times or less while RAS = V

18. Address (A0 - A8) may be changed once or less while CAS = V

and RAS = V

19. This is guaranteed by design. (t

SOH

COH

= t

SCA

CAC

- output transition time)

This parameter is not 100% tested.

¡ Semiconductor

MSM548263

13/40

Write Cycle Function Table

Code

RWM

BWM

FWM

LMR

LCR

DSF

RAS Falling Edge

Write Mask

DSF

CAS Falling Edge

Valid Data

Column Mask

Valid Data

Column Mask

Write Mask Data

Color Data

Function

Masked Write (New/Old)

Masked Block Write (New/Old)

Masked Flash Write (New/Old)

Normal Write

Block Write

Load Mask Register

Load Color Register

WRITE MASK DATA: "Low" = Mask, "High" = No Mask

Column Mask Data

DQ1 - 4

DQ1

DQ2

DQ3

DQ4

Column Mask Data

Column 0 (A0 = 0, A1 = 0)

Column 1 (A0 = 1, A1 = 0)

Column 2 (A0 = 0, A1 = 1)

Column 3 (A0 = 1, A1 = 1)

Low: Mask

High: No Mask

¡ Semiconductor

MSM548263

18/40

Fast Page Mode Read Modify Write Cycle

RAS

CAS

Address

RASP

RCD

CAS

RSH

CSH

CRP

RAD

RAL

Row

Column

RAH

ASC

CAH

ASR

"H" or "L"

DSF

RFH

FSC

CFH

FSR

RWH

WSR

DQ1 - 8

TRG

THH

THS

CWL

FHR

Column

ASC

CAH

FSC

CFH

Column

ASC

CAH

FSC

CFH

AWD

CAS

PRWC

CWD

RCS

AWD

CWL

AWD

Out

CAC

Out

CAC

Out

CAC

OEZ

OEA

OEZ

OEA

OEZ

OEA

¡ Semiconductor

MSM548263

24/40

Split Read Transfer

Note 1:

SE = "L"

Note 2: QSF = "L"-- Lower SAM (0 - 255) is active

QSF = "H"-- Upper SAM (256 - 511) is active

Note 3: Si is the SAM start address in before SRT
Note 4: STOP i and STOP j are programmable stop addresses

RAS

CAS

Address

DSF

DQ1 - 8

TRG

RAS

RCD

CAS

RSH

CSH

RAD

RAL

FSR

Row

SAM Start Sj

RAH

ASC

CAH

RFH

ASR

"H" or "L"

,,,

WSR

RWH

TLH

TLS

CTH

ATH

RTH

STOP i

S i

STOP

j - 1

STOP j

S j

STS

SDQ1 - 8

QSF

SQD

Note 2

Data Out

SOH

Data Out

SCA

SOH

SCA

Data Out

Note 2

SQD

SCP

SCC

,,,

Open

¡ Semiconductor

MSM548263

26/40

Masked Split Write Transfer

Note 1:

SE = "L"

Note 2: QSF = "L"-- Lower SAM (0 - 255) is active

QSF = "H"-- Upper SAM (256 - 511) is active

Note 3: Si is the SAM start address in before SWT
Note 4: STOP i and STOP j are programmable stop addresses

RAS

CAS

Address

DSF

DQ1 - 8

TRG

,,,

RAS

RCD

CAS

RSH

CSH

RAD

RAL

FSR

Row

SAM Start Sj

RAH

ASC

CAH

RFH

ASR

"H" or "L"

,,,

WSR

RWH

TLH

TLS

CTH

ATH

RTH

STOP i

S i

STOP

j - 1

STOP j

S j

STS

SDQ1 - 8

QSF

SQD

Note 2

Data In

SDS

Data In

SDH

Note 2

SQD

SCP

SCC

Data In

SDS

SDH

Mask Data

Open

¡ Semiconductor

MSM548263

28/40

PIN FUNCTIONS

Address Input: A0 - A8

The 18 address bits decode 8 bits of the 2,097,152 locations in the MSM548263 memory array. The
address bits are multiplexed to 9 address input pins (A0 - A8) as standard DRAM. 9 row address
bits are latched at the falling edge of RAS. The following 9 column address bits are latched at the
falling edge of CAS.

Row Address Strobe: RAS

RAS is a basic RAM control signal. The RAM port is in standby mode when the RAS level is
"high". As the standard DRAM's RAS signal function, RAS is the control input that latches the
row address bits, and a random access cycle begins at the falling edge of RAS.
In addition to the conventional RAS signal function, the level of the input signals CAS, TRG, WE
and DSF at the falling edge of RAS, determines the MSM548263 operation mode.

Column Address Strobe: CAS

As the standard DRAM's CAS signal function, CAS is the control input signal that latches the
column address input and the state of the special function input DSF to select in conjunction with
the RAS control, either read/write operations or the special block write feature on the RAM port
when the DSF is held "low" at the falling edge of RAS.
CAS also acts as a RAM port output enable signal.

Data Transfer/Output Enable: TRG

TRG is also a control input signal having multiple functions. As the standard DRAM's OE signal
function, TRG is used as an output enable control when TRG is "high" at the falling edge of RAS.
In addition to the conventional OE signal function, a data transfer operation is started between
the RAM port and the SAM port when TRG is "low" at the falling edge of RAS.

Write Per Bit/Write Enable: WE

WE is a control input signal having multiple functions. As the standard DRAM's WE signal
function, this is used to write data into the memory on the RAM port when WE is "high" at the
falling edge of RAS.
In addition to the conventional WE signal function, the WE determines the write-per-bit
function, when WE is "low" at the falling edge of RAS during RAM port operations.
The WE also determines the direction of data transfer between the RAM and SAM. When the WE
is "high" at the falling edge of RAS, the data is transferred from RAM to SAM (read transfer).
When the WE is "low" at the falling edge of RAS, the data is transferred SAM to RAM (write
transfer).

¡ Semiconductor

MSM548263

29/40

Write Mask Data/Data Input and Output: DQ1 - DQ8

In conventional write-per bit mode, the DQ pins function as mask data at the falling edge of RAS.
Data is written only to high DQ pins. Data on low DQ pins is masked and internal data is retained.
After that, they function as input/output pins similar to a standard DRAM.
In persistent write-per-bit mode, DQ pins are don't care at the falling edge of RAS. The mask data
are determined in the mask register load cycle.

Serial Clock: SC

SC is a main serial cycle control input signal. All operations of the SAM port are synchronized
with the serial clock SC. Data is shifted in or out of the SAM registers at the rising edge of SC. In
a serial read cycle, the output data becomes valid on the SDQ pins after the maximum specified
serial access time t

SCA

from the rising edge of SC.

In a serial write cycle, data on SDQ pins at the rising edge of SC are fetched into the SAM register.

Serial Enable: SE

The SE is a serial access enable control and serial read/write control signal. In a serial read cycle,
SE is used as an output control. In a serial write cycle, SE is used as a write enable control. When
SE is "high", serial access is disabled. However, the serial address pointer location is still
incremented when SC is clocked even when SE is "high".

Special Function Input: DSF

The DSF is latched at the falling edge of RAS and CAS. It allows for the selection of several RAM
ports and transfer operating modes. In addition to the conventional multiport DRAM, the special
functions consisting of flash write, block write, load/read color register, and split read/write
transfer can be invoked.

Special Function Output: QSF

QSF is an output signal, which during split register mode indicates which half of the split SAM
is being accessed. QSF "low" indicates that the lower split SAM (0 - 255) is being accessed. QSF
"high" indicates that the upper SAM (256 - 511) is being accessed.

Serial Input/Output: SDQ1 - SDQ8

Serial input/output mode is determined by the most recent read or write transfer cycle. When
a read transfer cycle is performed, the SAM port is in the output mode. When a write or pseudo
write transfer cycle is performed, the SAM port is switched from output mode to input mode.

¡ Semiconductor

MSM548263

30/40

OPERATION MODES

Table-1 shows the function truth table for a listing of all available RAM ports and transter
operation of MSM548263.
The RAM port and data transfer operations are determined by the state of CAS, TRG, WE and
DSF at the falling edge of RAS, and by the level of DSF at the falling edge of CAS.

Table-1. Function Truth Table

RASØ

Code

Address

CAS TRG WE DSF DSF

RASØ

CAS

Write Pers.

Color

Reset Reset

CBRR

CASØ

/WE

Mask W.M.

RASØ

W/IO

CASØ

Register

Function

CBR Refresh

(Register Reset)

STOP

CBRS

CBR Refresh

(Stop Register Set)

CBRN

CBR Refresh (No Reset)

Row

ROR

RAS Only Refresh

Row TAP WM1

Yes

No/ Load

MWT

Masked Write Transfer

Row TAP WM1

Yes

No/

MSWT

Masked Split

Write Transfer

Row TAP

Read Transfer

Row TAP

SRT

Split Read Transfer

Row

Column

WM1

Din, Dout

Yes

No/

RWM

Read/Write

(New/Old Mask)

Row

Column

WM1

Yes

No/

Use

BWM

Masked Block Write

(New/Old)

Row

WM1

Yes

No/

Use

FWM

Masked Flash Write

(New/Old)

Row

Column

Din, Dout

Read/Write

(No Mask)

Row

Use

Block Write

(No Mask)

Row

Set Load

LMR

Load Mask Register

(Old Mask Set)

Row

Load

LCR

Load Color Register

A2c - 8c

Column

A2c - 8c

Column

Select

Column

Select

Mask

Data

Color

Data

Use

Load

Use

Load

Use

Load

Use

Load

Use

Yes

Notes:

1. With CBRS and SAM operations use stop register
2. After LMR, RWM, BWM, FWM and MSWT, use old mask which can be reset by

CBRR.

¡ Semiconductor

MSM548263

31/40

If the DSF is "high" at the falling edge of RAS, special functions such as split transfer, flash write,
load mask register, load color register, CBRS and CBRN can be invoked.
If the DSF is "low" at the falling edge of RAS and "high" at the falling edge of CAS, the block write
feature can be invoked.

RAM PORT OPERATION

Extended RAM Read Cycle: RAS falling edge --- TRG = CAS = "H", DSF = "L"

CAS falling edge --- DSF = "L"

The MSM548263 offers an accelerated page mode cycle (EXTENDED PAGE MODE) by eliminating
output disable from CAS "high", and it allows CAS precharge time (t

) to occur without the

output data becoming invalid. This new data out operates (Extended data out) as any RAM read
or Page Mode Read, except data will be held valid after CAS goes "high", as long as RAS is "low".

RAM Write Cycle: RAS falling edge --- TRG = CAS = "H", DSF = "L"

CAS falling edge --- DSF = "L"

1) Write cycle with no mask: RAS falling edge -- WE = "H"

If WE is set "low" at the falling edge of CAS after RAS goes "low", a write cycle is excuted. If WE
is set "low" before the CAS falling edge, this cycle becomes an early write cycle, and all DQ pins
attain high impedance. All 8 data are latched on the falling edge of CAS.
If WE is set "low" after the CAS falling edge, this cycle becomes a late write cycle, and all 8 data
are latched on the falling edge of WE.

2) Write cycle with mask: RAS falling edge -- WE = "L"

If WE is set "low" at the falling edge of RAS, two modes of mask write can be invoked.
#1 In new mask mode mask data is loaded and used. The mask data on DQ1 - DQ8 is latched into
the write mask register at the falling edge of RAS. When the mask data is low, writing is inhibited
into the RAM and the mask data is high, data is written into the RAM. This mask data is in effect
during the RAS cycle. In page mode cycle the mask data is retained during page access.
#2 If a load mask register cycle (LMR) has been performed, the mask data is not loaded from DQ
pins, and the mask data stored in the mask register is persistently used.
This operation is known as persistent write mask, set by LMR and reset by CBRR.

¡ Semiconductor

MSM548263

32/40

Load/Read Color Register:

RAS falling edge --- CAS = TRG = WE = DSF = "H"
CAS falling edge --- DSF = "H"

The MSM548263 is provided with an on-chip 8-bit color register for use during the flash write or
block write operation. Each bit of the color register corresponds to one of the DRAM I/O blocks.
The data presented on the DQi lines is subsequently latched into the color register at the falling
edge of either CAS or WE whichever occurs later.
The read color register cycle is activated by holding WE "high" at the falling edge of CAS, and
throughout the remainder of the cycle. The data in the color register becomes valid on the DQi
lines after the specified access times from RAS and TRG are satisfied.
During the load/read color register cycle, the memory cells on the row address latched at the
falling edge of RAS are refreshed.

Load/Read Mask Register:

RAS falling edge --- CAS = TRG = WE = DSF = "H"
CAS falling edge --- DSF = "L"

The MSM548263 is provided with an on-chip 8-bit mask register for use during the mask write
cycle, flash write cycle, block write cycle, masked write transfer, and masked split write transfer.
Each bit of the mask register corresponds to one of the DRAM I/O blocks.
The data presented on the DQi lines is subsequently latched into the mask register at the falling
edge of either CAS or WE whichever occurs later.
The read mask register cycle is activated by holding WE "high" at the falling edge of CAS, and
throughout the remainder of the cycle. The data in the mask register becomes valid on the DQi
lines after the specified access times from RAS and TRG are satisfied.
During the load/read mask register cycle, the memory cells on the row address latched at the
falling edge of RAS are refreshed.

Flash Write: RAS falling edge --- CAS = TRG = DSF = "H", WE = "L"

Flash write allows for the data in the color register to be written into all the memory locations of
a selected row.
Each bit of the color register corresponds to one of the DRAM I/O blocks. The flash write
operation can be selectively controlled on an I/O basis in the same manner as the write per bit
operation. The mask data is the same as that of a RAM write cycle.

¡ Semiconductor

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Block Write: RAS falling edge --- CAS = TRG = "H", DSF = "L"

CAS falling edge --- DSF = "H"

Block write allows for the data in the color register to be written into 4 consecutive column
address locations, starting from a selected column address in a selected row.
The block write operation can be selectively controlled on an I/O basis, and a column mask
capability is also available. During a block write cycle, the 2 least significant column address
locations (A0C and A1C) are internally controlled, and only the 7 most significant column
addresses (A2C - A8C) are latched at the falling edge of CAS.
1) No mask block write: WE "high" at the falling edge of RAS

The data on 8 DQ pins is all cleared by the data of the color register.

2) Masked block write: WE "low" at the falling edge of RAS

The mask data is the same as that of a RAM write cycle.

SAM PORT OPERATION

Single Register Mode

High speed serial read or write operation can be performed through the SAM port independent
of the RAM port operation, except during read/write transfer cycles.
The preceding transfer operation determines the direction of data flow through the SAM port.
If the preceding transfer is a read transfer, the SAM port is in the output mode. If the preceding
transfer is write transfer, the SAM port is in the input mode.
Serial data can be read out of the SAM after a read transfer has been performed. The data is shifted
out of the SAM starting at any of the 512 bits locations.
The TAP location corresponds to the column address selected at the falling edge of CAS during
the read or write transfer cycle. The SAM registers are configured as a circular data register. The
data is shifted out sequentially. It starts from the selected TAP location at the most significant bit
(511), then wraps around to the least significant bit (0).

Split Register Mode

In split register mode data can be shifted into or out of one half of the SAM, while a split read or
split write transfer is being performed on the other half of the SAM.
Conventional (non split) read, or write transfer cycle must precede any split read or split write
transfers. The split read and write transfers will not change the SAM port mode set by the
preceding conventional transfer operation. In the split register mode, serial data can be shifted
in or out of one of the split SAM registers, starting from any at the 256 TAP locations, excluding
the last address of each split SAM the data is shifted in or out sequentially starting from the
selected TAP location at the most significant bit (255 or 511) of the first split SAM, and then the
SAM pointer moves to the TAP location selected for the second split SAM to shift data in or out
sequentially, starts from this TAP location at the most significant bit (511 or 255), and finally
wraps around to the least significant bit.

255

TAP

256 257

511

TAP

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DATA TRANSFER OPERATIONS

The MSM548263 features two types of bidirectional data transfer capability between RAM and
SAM.
1) Conventional (non split) transfer: 512 words by 8 bits of data can be loaded from RAM to SAM

(Read transfer), or from SAM to RAM (Write transfer).

2) Split transfer: 256 words by 8 bits of data can be loaded from the lower/upper half of the RAM

to the lower/upper half of the SAM (Split read transfer), or from the lower/upper half of SAM
to the lower/upper half of RAM (Split write transfer).

The conventional transfer and split transfer modes are controlled by the DSF input signal.
Data transfer are invoked by holding the TRG signal "low" at the falling edge of RAS.
The MSM548263 supports 4 types of transfer operations: Read transfer, Split read transfer, Write
transfer and Split write transfer as shown in the truth table. The type of transfer operation is
determined by the state of CAS, WE and DSF latched at the falling edge of RAS. During
conventional transfer operations, the SAM port is switched from input to output mode (Read
transfer), or output to input mode (Write transfer). It remains unchanged during split transfer
operation (Split read transfer or Split write transfer).
Both RAM and SAM are divided by the most significant row address (AX8), as shown in Figure
1. Therefore, no data transfer between AX8 = 0 side RAM and AX8 = 1 side RAM can be provided
through the SAM. Care must be taken if the split read transfer on AX8 = 1 side (or AX8 = 0 side)
is provided after the read transfer or the split read transfer, is provided on AX8 = 0 side (or AX8
= 1 side).

Figure 1. RAM and SAM Configuration

256 ¥ 256 ¥ 8

Memory

Array

256 ¥ 256 ¥ 8

Memory

Array

256 ¥ 256 ¥ 8

Memory

Array

256 ¥ 256 ¥ 8

Memory

Array

Serial Decoder

Upper SAM

256

Lower SAM

256

Upper SAM

256

Lower SAM

256

AX8 = 0

AX8 = 1

SAM I/O Buffer

SDQ1 - 8

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Read Transfer: RAS falling edge --- CAS = WE = "H", TRG = DSF = "L"

Read transfer consists of loading a selected row of data from the RAM into the SAM register. A
read transfer is invoked by holding CAS "high", TRG "low", WE "high", and DSF "low" at the
falling edge of RAS. The row address selected at the falling edge of RAS determines the RAM row
to be transferred into the SAM. The transfer cycle is completed at the rising edge of TRG. When
the transfer is completed, the SAM port is set into the output mode. In a read/real time read
transfer cycle, the transfer of a new row of data is completed at the rising edge of TRG, and this
data becomes valid on the SDQ lines after the specified access time t

SCA

from the rising edge of

the subsequent SC cycles. The start address of the serial pointer of the SAM is determined by the
column address selected at the falling edge of CAS. In a read transfer cycle (which is preceded
by a write transfer cycle), SC clock must be held at a constant V

or V

after the SC high time

has been satisfied. A rising edge of the SC clock must not occur until after the specified delay t

TSD

from the rising edge of TRG.
In a real time read transfer cycle (which is preceded by another read transfer cycle), the previous
row data appears on the SDQ lines until the TRG signal goes "high", and the serial access time
t

SCA

for the following serial clock is satisfied. This feature allows for the first bit of the new row

of data to appear on the serial output as soon as the last bit of the previous row has been strobed
without any timing loss. To make this continuous data flow possible, the rising edge of TRG must
be synchronized with RAS, CAS, and the subsequent rising edge of SC (t

RTH

, t

CTH

, and t

TSL

TSD

must be satisfied).

Masked Write Transfer: RAS falling edge --- CAS = "H", TRG = WE = DSF = "L"

Write transfer cycle consists of loading the content of the SAM register into a selected row of the
RAM. This write transfer is the same as a mask write operation in RAM, so new and persistent
(old) mask mode can be supported. (Masked write transfer)
If the SAM data to be transferred must first be loaded through the SAM, a Masked write transfer
operation (all DQ pins "low" at falling edge of RAS) must precede the write transfer cycles. A
masked write transfer is invoked by holding CAS "high", TRG "low", WE "low" and DSF "low"
at the falling edge of RAS. The row address selected at the falling edge of RAS determines the
RAM row address into which the data will be transferred. The column address selected at the
falling edge of CAS determines the start address of the serial pointer of the SAM. After the write
transfer is completed, the SDQ lines are set in the input mode so that serial data synchronized
with the SC clock can be loaded.
When consecutive write transfer operations are performed, new data must not be written into
the serial register until the RAS cycle of the preceding write transfer is completed. Consequently,
the SC clock must be held at a constant V

or V

during the RAS cycle. A rising edge of the SC

clock is only allowed after the specified delay t

CSD

from the falling edge of the CAS, at which time

a new row of data can be written in the serial register.
Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to the
other address of RAM by write transfer cycle. However, the address to write data must be the
same as that of the read transfer cycle (row address AX8).

¡ Semiconductor

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Split Data Transfer and QSF

The MSM548263 features a bidirectional split data transfer capability between the RAM and
SAM. During split data transfer operation, the serial register is split into two halves which can
be controlled independently. Split read or split write transfer operation can be performed to or
from one half of the serial register, while serial data can be shifted into or out of the other half of
the serial register. The most significant column address location (A8C) is controlled internally to
determines which half of the serial register will be reloaded from the RAM. QSF is an output
which indicates which half of the serial register is in an active state. QSF changes state when the
last SC clock is applied to active split SAM.

Split Read Transfer: RAS falling edge --- CAS = WE = DSF = "H", TRG = "L"

The MSM548263 supports two types of split register operation.
#1 Normal split register operation
#2 Boundary split register operation using programmable SAM stops described later.
Normal split read transfer consists of loading 256 words by 8 bits of data from a selected row of
the split RAM into the corresponding non-active split SAM register. Serial data can be shifted out
from the other half of the split SAM register simultaneously. During split read transfer operation,
the RAM port input clocks do not have to be synchronized with the serial clock SC, thus
eliminating timing restrictions as in the case of real time read transfers. A split read transfer can
be performed after a delay of t

STS

from the change of state of the QSF output is satisfied.

Conventional (non-split) read transfer operation must precede split read transfer cycles.

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Masked Split Write Transfer: RAS falling edge --- CAS = DSF = "H", TRG = WE = "L"

Split write transfer consists of loading 256 words by 8 bits of data from the non-active split SAM
register into a selected row of the corresponding split RAM. Serial data can be shifted into the
other half of the split SAM register simultaneously. During split write transfer operation, the
RAM port input clocks do not have to be synchronized with the serial clock SC, thus allowing
for real time transfer. This operation is the same as a mask write operation in RAM, so new and
persistent mode can be supported.
A split write transfer can be performed after a delay of t

STS

from the change of state of the QSF

output is satisfied.
A masked write transfer operation must precede split write transfer. The purpose is to switch the
SAM port from output mode to input mode, and to set the initial TAP location prior to split write
transfer operations.

Programmable SAM Stops in Split Transfer Cycle

The MSM548263 has a boundary split register operation using programmable stops. If a CBRS
cycle has been performed, the split transfer cycle performs the boundary operation.
Figure 2 shows an example of a boundary split register (4 stop points). The stop points define a
SAM location at which the access will change from one half of the SAM to the other half (at the
TAP address).

TAP1

255

TAP3

Lower SAM

256

511

Upper SAM

TAP2

S.T. (TAP2)

S.T. (TAP3)

Figure 2. Example of Boundary Split Register

¡ Semiconductor

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SAM Stop Set Cycle (CBRS): RAS falling edge --- CAS = "L", WE = "L", DSF = "H"

SAM Stop location data (boundaries) are latched from address inputs at the falling edge of RAS.
To determine the boundary A4 - A7 are used, and A0 - A3, and A8 are ignored.
Once the CBRS is executed, the programmable SAM stop operation continues until CBRR.

SAM Stop Boundary Table

Number of Stop Points

Address

256

128

Size of Partition

Register Reset Cycle (CBRR): RAS falling edge --- CAS = "L", WE = "H", DSF = "L"

A CBRR can reset the programmable SAM stop operation, and persistent mask write operation.
The CBRR will take effect immediately; it doesn't require a split transfer cycle.

POWER UP

Power must be applied to the RAS and TRG input signals to pull them "high" before, or at the
same time as, the V

supply is turned on. After power-up, a pause of 200 ms minimum is

required with RAS and TRG held "high". After the pause, a minimum of 8 RAS and 8 SC dummy
cycles must be performed to stabilize the internal circuitry, before valid read, write or transfer
operations can begin. During the initialization period, the TRG signal must be held "high". If the
internal refresh counter is used, a minimum 8 CAS before RAS cycles are required instead of 8
RAS cycles.

(NOTE) INITIAL STATE AFTER POWER UP

The initial state can not be guaranteed for various power up conditions and input signal levels.
Therefore, it is recommended that the initial state be set (ex. Perform a CBRR cycle to select Non
Persistent Write-per-bit mode) after the initialization of the device is performed and before valid
operations begin.

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