¡ Semiconductor

MSM7578H/7578V/7579

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¡ Semiconductor

MSM7578H/7578V/7579

Single Rail CODEC

GENERAL DESCRIPTION

The MSM7578 and MSM7579 are single-channel CODEC CMOS ICs for voice signals ranging
from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, these devices are
particularly optimized for telephone terminals in digital wireless systems and ISDN systems.
The devices use the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output signal can directly drive a piezoelectric type handset receiver.

FEATURES

· Single power supply: +5.0 V

· Low power consumption

Operating mode:

25 mW Typ. 47 mW Max.

= 5 V

Power down mode:

0.05 mW Typ. 0.3 mW Max.

= 5 V

· ITU-T Companding law

MSM7578H:

m-law

MSM7579:

A-law

MSM7578V:

m/A-law pin-selectable

· Built-in PLL eliminates a master clock
· Serial data rate: 64/128/256/512/1024/2048 kHz

96/192/384/768/1536/1544/200 kHz

· Adjustable transmit gain
· Built-in reference voltage supply
· Directly drive a line transformer of 600 W
· The 16-pin DIP and 24-pin SOP package products provide pin compatibility with the MSM7508B/

7509B

· The 20-pin SSOP package products have 1/3 the foot print of conventional products
· Package options:

16-pin plastic DIP (DIP16-P-300-2.54)

(Product name : MSM7578HRS)
(Product name : MSM7579RS)
(Product name : MSM7578VRS)

24-pin plastic SOP (SOP24-P-430-1.27-K)

(Product name : MSM7578HGS-K)
(Product name : MSM7578VGS-K)
(Product name : MSM7579GS-K)

20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name : MSM7578HMS-K)

(Product name : MSM7579MS-K)
(Product name : MSM7578VMS-K)

E2U0017-28-81

This version: Aug. 1998

Previous version: Nov. 1996

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PIN CONFIGURATION (TOP VIEW)

SGC

AOUT

PDN

RSYNC

AIN+

AIN

GSX

(ALAW)*

XSYNC

16-Pin Plastic DIP

PCMIN

PCMOUT

SGC

AOUT

PDN

AIN+

AIN

GSX

(ALAW)*

BCLK

NC : No connect pin

RSYNC

PCMIN

XSYNC

PCMOUT

NC : No connect pin

BCLK

SGC

AOUT

PDN

RSYNC

AIN+

AIN

GSX

XSYNC

PCMIN

PCMOUT

BCLK

(ALAW)*

24-Pin Plastic SOP

20-Pin Plastic SSOP

* The ALAW pin is only applied to the MSM7578VRS/MSM7578VGS-K/MSM7578VMS-K.

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PIN AND FUNCTIONAL DESCRIPTIONS

AIN+, AIN, GSX

Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN is an inverting input to the op-amp; GSX is
connected to the output of the op-amp and is used to adjust the level, as shown below.
When not using AIN and AIN+, connect AIN to GSX and AIN+ to SG. During power saving
and power down modes, the GSX output is at AG voltage.

AIN
AIN+

Analog input

1) Inverting input type

R1 : variable
R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)

Gain = R2/R1 £ 10

GSX

AIN+
AIN

2) Non inverting input type

R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)

Gain = 1 + R4 / R3 £ 10

GSX

Analog input

Analog signal ground.

AOUT

Analog output.
The output signal has a maximum amplitude of 2.4 V

above and below the signal ground

voltage (V

/2).

The output load resistance is a minimum of 600 W.
During power saving, or power down mode, the output of AOUT is at the voltage level of the
signal ground.

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Power supply for +5 V.

PCMIN

PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at a falling edge of the BCLK signal and latched into the internal register
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.

BCLK

Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the
power saving state.

RSYNC

Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLK. The frequency should be 8 kHz

50 ppm to guarantee the

AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 kHz

2 kHz, but the electrical characteristics in this specification are

not guaranteed.

XSYNC

Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit
synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing
signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.
The frequency should be 8 kHz

50 ppm to guarantee the AC characteristics which are mainly

the frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 kHz

2 kHz, but the electrical characteristics in this specification are

not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.

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Ground for the digital signal circuits.
This ground is separate from the analog signal ground. The DG pin must be connected to the AG
pin on the printed circuit board to make a common analog ground.

PDN

Power down control signal.
A logic "0" level drives both transmit and receive circuits to a power down state.

PCMOUT

PCM signal output.
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising
edge of the BCLK signal.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down mode.
A pull-up resistor must be connected to this pin because its output is configured as an open drain.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7579 (A-law) outputs the character signal, inverting the even bits.

Input/Output Level

+Full scale

Full scale

PCMIN/PCMOUT

MSM7578H (

m-law)

MSD

MSM7579 (A-law)

MSD

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Signal ground voltage output.
The output voltage is 1/2 of the power supply voltage.
The output drive current capability is

300 mA.

This pin provides the SG level for CODEC peripherals.
This output voltage level is undefined during power saving or power down mode.

SGC

Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.

ALAW

Control signal input of the companding law selection.
Provides only for the MSM7578VRS/7578VGS-K/7578VMS-K. The CODEC will operate in the
m-law when this pin is at a logic "0" level and the CODEC will operate in the A-law when this pin
is at a logic "1" level. The CODEC operates in the m-law if the pin is left open, since the pin is
internally pulled down.

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ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage

Analog Input Voltage

Digital Input Voltage

Storage Temperature

Symbol

AIN

DIN

STG

Condition

Rating

0 to 7

0.3 to V

+ 0.3

0.3 to V

+ 0.3

55 to +150

Unit

°C

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Power Supply Voltage

Analog Input Voltage

Input High Voltage

Input Low Voltage

Clock Frequency

Sync Pulse Frequency

Clock Duty Ratio

Digital Input Rise Time

Digital Input Fall Time

Transmit Sync Pulse Setting Time

Receive Sync Pulse Setting Time

Sync Pulse Width

PCMIN Set-up Time

PCMIN Hold Time

Digital Output Load

Analog Input Allowable DC Offset

Allowable Jitter Width

AIN

off

Condition

Connect AIN and GSX

XSYNC, RSYNC, BCLK,

PCMIN, PDN, ALAW

BCLK

XSYNC, RSYNC

BCLK

XSYNC, RSYNC, BCLK,

PCMIN, PDN, ALAW

BCLKÆXSYNC, See Timing Diagram

XSYNC, RSYNC

Pull-up resistor

Transmit gain stage, Gain = 10

XSYNCÆBCLK, See Timing Diagram

BCLKÆRSYNC, See Timing Diagram

RSYNCÆBCLK, See Timing Diagram

Transmit gain stage, Gain= 1

XSYNC, RSYNC, BCLK

Min.

Typ.

Max.

Unit

4.75

2.2

64, 128, 256, 512, 1024,

2048, 96, 192, 384, 768,

1536, 1544, 200

6.0

100

1 BCLK

100

0.5

100

8.0

5.25

2.4

0.8

9.0

100

+10

+100

100

kHz

Voltage must be fixed

Operating Temperature

+25

°C

+85

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ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

Parameter

Power Supply Current

Input High Voltage

Input Low Voltage

High Level Input Leakage Current

Low Level Input Leakage Current

Digital Output Low Voltage

Digital Output Leakage Current

Input Capacitance

Symbol

DD1

DD2

DD3

Condition

Operating mode, No signal

Power-save mode, PDN = 1,

XSYNC Æ OFF

Pull-up resistance > 500 W

Min.

2.2

0.0

Typ.

0.01

1.2

0.2

Max.

0.05

3.0

0.8

2.0

0.5

0.4

Unit

Power-down mode, PDN = 0

= +5 V ±5%, Ta = 30°C to +85°C)

Analog Input Resistance

AIN+, AIN

Transmit Analog Interface Characteristics

Input Resistance

Output Load Resistance

Output Load Capacitance

Output Amplitude

Offset Voltage

INX

LGX

OGX

OSGX

AIN+, AIN

Gain = 1

1.2

+1.2

+20

GSX with respect to SG

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

= +5 V to ±5%, Ta = 30°C to +85°C)

Receive Analog Interface Characteristics

Output Load Resistance

Output Load Capacitance

LAO

0.6

Output Amplitude

Offset Voltage

OAO

OSAO

1.2

100

+1.2

+100

AOUT with respect to SG

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

= +5 V to ±5%, Ta = 30°C to +85°C)

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AC Characteristics

Condition

= +5 V ±5%, Ta = 30°C to +85°C)

Parameter

Symbol

Min.

Typ.

Max.

Unit

Transmit Frequency Response

Loss T1

Level

(dBm0)

Freq.

(Hz)

Loss T2

300

0.15

+0.07

+0.20

Loss T3

1020

Reference

Loss T4

2020

0.15

0.04

+0.20

Loss T5

3000

0.15

+0.06

+0.20

Loss T6

3400

0.4

0.80

Receive Frequency Response

Loss R1

300

0.15

0.03

+0.20

Loss R2

1020

Reference

Loss R3

2020

0.15

0.02

+0.20

Loss R4

3000

0.15

+0.15

+0.20

Loss R5

3400

0.0

0.4

0.80

SD T1

SD T2

SD T3

Transmit Signal to Distortion Ratio

1020

SD T4

SD T5

SD R1

SD R2

SD R3

Receive Signal to Distortion Ratio

1020

SD R4

33.5

SD R5

Transmit Gain Tracking

GT T1

0.3

+0.01

+0.3

GT T2

Reference

GT T3

1020

0.3

+0.3

GT T4

0.6

0.13

+0.6

GT T5

1.2

0.15

+1.2

Receive Gain Tracking

GT R1

0.3

+0.3

GT R2

Reference

GT R3

1020

0.3

+0.10

+0.3

GT R4

0.6

+0.20

+0.6

GT R5

1.2

+0.25

+1.2

*1 Psophometric filter is used
*2 Upper is specified for the MSM7578H, lower for the MSM7579

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AC Characteristics (Continued)

Absolute Level (Initial Difference)

Nidle T

72.5

70.5

dBmOp

Nidle R

AV T

0.5803

0.6007

0.6218

AV R

0.5803

0.6007

0.6218

Vrms

1020

Absolute Delay

AV Tt

0.2

+0.2

AV Rt

0.2

+0.2

1020

0.60

A to A

BCLK

= 64 kHz

Transmit Group Delay

tgd T1

0.19

0.75

tgd T2

0.11

0.35

tgd T3

0.02

0.125

tgd T4

0.05

0.125

0.07

tgd T5

0.75

Receive Group Delay

0.00

0.75

0.00

0.125

0.09

0.125

0.12

0.75

Idle Channel Noise

AIN = SG

*1 *3

*1 *2

= 5.0 V

Ta = 25°C

= +5 V

±5%

Ta = 30

to 85°C

Absolute Level

(Deviation of Temperature and Power)

500

600

1000

2600

2800

Crosstalk Attenuation

CR T

CR R

1020

TRANS Æ RECV

RECV Æ TRANS

tgd R1

tgd R2

tgd R3

tgd R4

tgd R5

500

600

1000

2600

2800

0.35

Condition

= +5 V ±5%, Ta = 30°C to +85°C)

Parameter

Symbol

Min.

Typ.

Max.

Unit

Level

(dBm0)

Freq.

(Hz)

*1 Psophometric filter is used
*2 Upper is specified for the MSM7578H, lower for the MSM7579
*3 MSM7578H: All "1", MSM7579: "11010101"
*4 Minimum value of the group delay distortion

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AC Characteristics (Continued)

DIS

4.6 kHz to

Digital Output Delay Time

200

XD1

200

XD2

200

XD3

200

Discrimination

0 to

4000 Hz

= 100 pF

300 to

37.5

dBmO

Out-of-band Spurious

4.6 kHz to

IMD

fa = 470

dBmO

Intermodulation Distortion

2fa fb

PSR T

0 to

Power Supply Noise Rejection Ratio

50 mV

PSR R

72 kHz

3400

fb = 320

50 kHz

100 kHz

Condition

= +5 V ±5%, Ta = 30°C to +85°C)

Parameter

Symbol

Min.

Typ.

Max.

Unit

Level

(dBm0)

Freq.

(Hz)

*5 The measurement under idle channel noise

¡ Semiconductor

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TIMING DIAGRAM

PCM Data Input/Output Timing

BCLK

XSYNC

PCMOUT

MSD

XD1

XD2

XD3

BCLK

RSYNC

PCMIN

MSD

Transmit Timing

Receive Timing

When t

£ 1/2 · Fc, the Delay of the MSD bit is defined as t

XD1

When t

£ 1/2 · Fc, the Delay of the MSD bit is defined as t

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APPLICATION CIRCUIT

PCMOUT

AIN

GSX

Analog input

AOUT

10 mF

PCM signal output

PCM data input

PCM Shift Clock input

8 kHz SYNC signal input

Power Down control input

0.1 mF

1 kW

"1" = Operation
"0" = Power down

MSM7578H/7579

0 to 10 W

AIN+

PCMIN

BCLK

Analog output

5 V

XSYNC

PDN

SGC

0 V

+5 V

RSYNC

1 mF

Analog interface

Digital interface

The analog output signal has an amplitude of

1.2 V above and below the offset voltage level of

/2.

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RECOMMENDATIONS FOR ACTUAL DESIGN

· To assure proper electrical characteristics, use bypass capacitors with excellent high frequency

characteristics for the power supply and keep them as close as possible to the device pins.

· Connect the AG pin and the DG pin each other as close as possible. Connect to the system

ground with low impedance.

· Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an

IC socket is unavoidable, use the short lead type socket.

· When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave

source such as power supply transformers surround the device.

· Keep the voltage on the V

pin not lower than 0.3 V even instantaneously to avoid latch-

up phenomenon when turning the power on.

· Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)

power supply to avoid erroneous operation and the degradation of the characteristics of these
devices.

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(Unit : mm)

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

SOP24-P-430-1.27-K

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more
0.58 TYP.

Mirror finish

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(Unit : mm)

Notes for Mounting the Surface Mount Type Package

SSOP20-P-250-0.95-K

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more
0.18 TYP.

Mirror finish

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