ChipFind - документация

Электронный компонент: 0X9160

Скачать:  PDF   ZIP
Oxford Semiconductor Ltd.
69 Milton Park, Abingdon, Oxon, OX14 4RX, UK
Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141
Oxford Semiconductor 1999
OX9160 Data Sheet Revision 1.1 Feb. 1999
Part No. OX9160-TQC33-A
F
EATURES
33MHz, 32-bit target PCI controller.
Fully PCI 2.2 and PCI Power Management 1.0
compliant.
8- or 32-bit pass-through Local bus.
IEEE1284 parallel port.
Parallel port supports EPP mode for maximum data
transfer rate to printers, removable drives etc.
Most operations complete within one PCI frame (no
retries).
Supports shared interrupts
12 multi-purpose I/O pins which can be configured as
interrupt input pins.
EEPROM interface for optional reconfiguration.
Local bus operation via I/O or memory mapping.
Local bus supports Intel or Motorola mode signalling.
Existing driver support for common I/O solutions.
On-chip oscillator.
5.0V operation.
Low power CMOS.
160 TQFP package.
D
ESCRIPTION
The OX9160 is a low-cost, general purpose PCI bridge
solution designed to ease the migration to PCI of parallel
port cards and instrumentation devices. It is configurable to
provide either a Local bus interface or a bi-directional
parallel port.
Using the local bus function, legacy devices can be easily
accessed throught the target PCI interface, which is
compliant with version 2.2 of the PCI Bus Specification and
version 1.0 of PCI Power Management Specification. All
reads and writes are completed with a minimum of PCI wait
states, which ensures lower PCI bus occupancy than most
similar PCI bridge solutions.
The local bus can be configured to operate with either 8- or
32-bit data, using either Intel x86 style or Motorola style
signalling.
Alternatively the local bus can be disabled in favour of an
integrated IEEE 1284 EPP parallel port. The parallel port is
an IEEE 1284-compliant host interface, which supports
SPP, PS2 (bidirectional) and EPP modes.
The local Bus function is extremely flexible, allowing the
designer to customize the addressable space, divide it into
chip-select regions, access devices via I/O or memory
space mapping, and adjust the timings of all operations.
The default register values have been selected to support
many standard peripheral chips such as I/O controllers and
other ISA-type devices, however all such parameters can
be overwritten using an optional Microwire
TM
serial
EEPROM.
OX9160
PCI Peripheral Bridge with
EPP Parallel Port & 8/32 bit local bus
Data Sheet Revision 1.1 Page 2
OX9160
OXFORD SEMICONDUCTOR LTD.
C
ONTENTS
1 BLOCK DIAGRAM ......................................................................................................................................3
2 PIN INFORMATION.....................................................................................................................................4
3 PIN DESCRIPTIONS ...................................................................................................................................5
4 PCI TARGET CONTROLLER.....................................................................................................................8
4.1
OPERATION ...............................................................................................................................................................8
4.2
CONFIGURATION SPACE..........................................................................................................................................8
4.2.1
PCI CONFIGURATION SPACE REGISTER MAP.....................................................................................................9
4.3
ACCESSING LOGICAL FUNCTIONS........................................................................................................................ 10
4.3.1
PCI ACCESS TO 8-BIT LOCAL BUS...................................................................................................................... 10
4.3.2
PCI ACCESS TO 32-BIT LOCAL BUS.................................................................................................................... 11
4.3.3
PCI ACCESS TO PARALLEL PORT ...................................................................................................................... 11
4.4
ACCESSING LOCAL CONFIGURATION REGISTERS.............................................................................................. 12
4.4.1
LOCAL CONFIGURATION AND CONTROL REGISTER `LCC' (OFFSET 0X00) ..................................................... 12
4.4.2
MULTI-PURPOSE I/O CONFIGURATION REGISTER `MIC' (OFFSET 0X04) ......................................................... 13
4.4.3
LOCAL BUS TIMING PARAMETER REGISTER 1 `LT1' (OFFSET 0X08):............................................................... 14
4.4.4
LOCAL BUS TIMING PARAMETER REGISTER 2 `LT2' (OFFSET 0X0C): .............................................................. 16
4.4.5
GLOBAL INTERRUPT STATUS AND CONTROL REGISTER `GIS' (OFFSET 0X1C)............................................. 17
4.5
PCI INTERRUPTS..................................................................................................................................................... 18
4.6
POWER MANAGEMENT........................................................................................................................................... 19
5 LOCAL BUS...............................................................................................................................................20
5.1
OVERVIEW ............................................................................................................................................................... 20
5.2
OPERATION ............................................................................................................................................................. 20
5.3
CONFIGURATION & PROGRAMMING...................................................................................................................... 21
5.4
CLOCK REFERENCES ............................................................................................................................................. 21
6 BIDIRECTIONAL PARALLEL PORT.......................................................................................................22
6.1
OPERATION AND MODE SELECTION ..................................................................................................................... 22
6.1.1
SPP MODE ........................................................................................................................................................... 22
6.1.2
PS2 MODE............................................................................................................................................................ 22
6.1.3
EPP MODE ........................................................................................................................................................... 22
6.1.4
ECP MODE (NOT SUPPORTED) .......................................................................................................................... 22
6.2
PARALLEL PORT INTERRUPT ................................................................................................................................ 22
6.3
REGISTER DESCRIPTION........................................................................................................................................ 23
6.3.1
PARALLEL PORT DATA REGISTER `PDR' ........................................................................................................... 23
6.3.2
DEVICE STATUS REGISTER `DSR' ...................................................................................................................... 23
6.3.3
DEVICE CONTROL REGISTER `DCR'................................................................................................................... 24
6.3.4
EPP ADDRESS REGISTER `EPPA'....................................................................................................................... 24
6.3.5
EPP DATA REGISTERS `EPPD1-4'....................................................................................................................... 24
6.3.6
EXTENDED CONTROL REGISTER `ECR'............................................................................................................. 24
7 SERIAL EEPROM......................................................................................................................................25
7.1
SPECIFICATION ....................................................................................................................................................... 25
7.2
EEPROM DATA ORGANISATION............................................................................................................................. 25
7.2.1
ZONE0: HEADER.................................................................................................................................................. 25
7.2.2
ZONE1: LOCAL CONFIGURATION REGISTERS................................................................................................... 26
7.2.3
ZONE2: IDENTIFICATION REGISTERS ................................................................................................................ 27
7.2.4
ZONE3: PCI CONFIGURATION REGISTERS........................................................................................................ 27
8 OPERATING CONDITIONS......................................................................................................................28
9 DC ELECTRICAL CHARACTERISTICS..................................................................................................28
Data Sheet Revision 1.1 Page 3
OX9160
OXFORD SEMICONDUCTOR LTD.
9.1
NON-PCI I/O BUFFERS............................................................................................................................................. 28
9.2
PCI I/O BUFFERS ..................................................................................................................................................... 29
10 AC ELECTRICAL CHARACTERISTICS ..............................................................................................30
10.1
PCI BUS.................................................................................................................................................................... 30
10.2
LOCAL BUS.............................................................................................................................................................. 30
11 TIMING WAVEFORMS..........................................................................................................................32
12 PACKAGE INFORMATION...................................................................................................................37
13 ORDERING INFORMATION .................................................................................................................37
1 B
LOCK DIAGRAM
Internal Data / control bus
LBD[7:0]
LBA[7:0]
LBCS[3:0]
LBWR#
LBRD#
LBRST
Interrupt
logic
PCI
interface
AD[31:0]
C/BE[3:0]#
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
CLK
PAR
SERR#
PERR#
IDSEL
RST#
INTA#
PME#
Config.
interface
MODE[1:0]
XTALO
XTALI
Crystal Oscillator
UART_Ck_Out
LBCLK
EE_DO
EE_DI
EEPROM
interface
EE_CK
EE_CS
MIO[11:0]
Parallel
port
PD[7:0]
ACK#
PE
BUSY
SLCT
ERR#
SLIN#
INIT#
AFD#
STB#
Local Bus
Figure 1 : OX9160 block diagram
Data Sheet Revision 1.1 Page 4
OX9160
OXFORD SEMICONDUCTOR LTD.
2 P
IN
I
NFORMATION
Mode `00': 8-bit local bus
LBA0
LBRST
LBRST#
MIO7
MIO6
MIO5
MIO4
MIO3
MIO2
MIO1
MIO0
INTA#
NC
RST#
GND
CLK
VDD
AD20
VDD
GND
AD19
AD18
AD31
AD30
AD29
GND
AD28
AD27
AD26
GND
VDD
AD25
AD24
C/BE3#
IDSEL
AD23
GND
AD22
AD21
PME#
120 119
118 117
116 115 114
113 112
111 110
109 108
107 106 105
104
85
84 83 82
81
102 101
100 99 98
97 96
95 94
93 92
91 90 89
88 87
86
103
LBA1 LBA2
LBA3 LBCS0#
LBCS1# LBCS2# LBCS3#
LBRD# LBWR#
VDD GND LBCLK
LBA4
LBA5 LBA6 LBA7
VDD
GND
GND
GND
NC
NC
LBDOUT LBD0
GND
LBD1
LBD2 LBD3
VDD GND
LBD4 LBD5 LBD6
LBD7 MIO8
MIO9 MIO10 MIO11
GND
GND
AD17
AD16
C/BE2#
FRAME#
IRDY# TRDY#
DEVSEL#
GND
STOP# PERR#
SERR#
PAR
C/BE1#
AD15
AD14 AD13
GND
AD2 AD1
AD0
EE_CS
EE_DO
AD12 AD11
GND VDD
AD10 AD9
GND AD8
C/BE0#
AD7
AD6 GND VDD AD5 AD4 AD3 GND
VDD
1
2 3
4 5
6 7
8 9 10
11 12
13 14
15 16 17
36 37
38 39
40
19
20 21
22 23
24 25 26
27 28
29 30
31 32 33
34 35
18
OX9160-TQC33-A
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
156
157
158
159
160
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
138
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
45
44
43
42
41
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
63
NC
NC
NC
NC
GND
GND
GND
GND
VDD
XTL_Ck_Out
GND
GND
GND
GND
GND
VDD
XTLO
Mode0
Mode1
NC
EE_DI
EE_CK
GND
GND
GND
NC
NC
VDD
GND
NC
NC
NC
NC
GND
GND
GND
GND
GND
GND
XTLI
Mode `11': 32-bit local bus
LBA0
LBRST
LBRST#
MIO7
MIO6
MIO5
MIO4
MIO3
MIO2
MIO1
MIO0
INTA#
NC
RST#
GND
CLK
VDD
AD20
VDD
GND
AD19
AD18
AD31
AD30
AD29
GND
AD28
AD27
AD26
GND
VDD
AD25
AD24
C/BE3#
IDSEL
AD23
GND
AD22
AD21
PME#
120 119
118 117
116 115 114
113 112
111 110
109 108
107 106 105
104
85
84 83 82
81
102 101
100 99 98
97 96
95 94
93 92
91 90 89
88 87
86
103
LBA1 LBA2
LBA3 LBCS0#
LBCS1# LBCS2# LBCS3#
LBRD# LBWR#
VDD GND LBCLK
LBA4
LBA5 LBA6 LBA7
VDD
LBD9
LBD10
LBD12
LBD13
LBD14
LBDOUT LBD0
LBD11
LBD1
LBD2 LBD3
VDD GND
LBD4 LBD5 LBD6
LBD7 MIO8
MIO9 MIO10 MIO11
LBD8
GND
AD17
AD16
C/BE2#
FRAME#
IRDY# TRDY#
DEVSEL#
GND
STOP# PERR#
SERR#
PAR
C/BE1#
AD15
AD14 AD13
GND
AD2 AD1
AD0
EE_CS
EE_DO
AD12 AD11
GND VDD
AD10 AD9
GND AD8
C/BE0#
AD7
AD6 GND VDD AD5 AD4 AD3 GND
VDD
1
2 3
4 5
6 7
8 9 10
11 12
13 14
15 16 17
36 37
38 39
40
19
20 21
22 23
24 25 26
27 28
29 30
31 32 33
34 35
18
OX9160-TQC33-A
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
156
157
158
159
160
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
138
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
45
44
43
42
41
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
63
LBD15
LBA8
LBA9
LBA10
LBA11
NC
NC
NC
VDD
XTL_Ck_Out
GND
NC
LBD16
LBD17
LBD18
VDD
XTLO
Mode0
Mode1
NC
EE_DI
EE_CK
GND
LBD19
LBD20
LBD21
LBD22
VDD
GND
LBD23
LBD24
LBD25
LBD26
LBD27
LBD28
LBD29
LBD30
LBD31
GND
XTLI
Mode `01': Parallel port
PE
ACK#
NC
MIO7
MIO6
MIO5
MIO4
MIO3
MIO2
MIO1
NC
INTA#
NC
RST#
GND
CLK
VDD
AD20
VDD
GND
AD19
AD18
AD31
AD30
AD29
GND
AD28
AD27
AD26
GND
VDD
AD25
AD24
C/BE3#
IDSEL
AD23
GND
AD22
AD21
PME#
120 119
118 117
116 115 114
113 112
111 110
109 108
107 106 105
104
85
84 83 82
81
102 101
100 99 98
97 96
95 94
93 92
91 90 89
88 87
86
103
BUSY SLCT
ERR# NC
NC NC NC
NC NC
VDD GND NC
SLIN#
INIT# AFD# STB#
VDD
GND
GND
GND
NC
NC
NC PD0
GND
PD1
PD2 PD3
VDD GND
PD4 PD5 PD6
PD7 MIO8
MIO9 MIO10 MIO11
GND
GND
AD17
AD16
C/BE2#
FRAME#
IRDY# TRDY#
DEVSEL#
GND
STOP# PERR#
SERR#
PAR
C/BE1#
AD15
AD14 AD13
GND
AD2 AD1
AD0
EE_CS
EE_DO
AD12 AD11
GND VDD
AD10 AD9
GND AD8
C/BE0#
AD7
AD6 GND VDD AD5 AD4 AD3 GND
VDD
1
2 3
4 5
6 7
8 9 10
11 12
13 14
15 16 17
36 37
38 39
40
19
20 21
22 23
24 25 26
27 28
29 30
31 32 33
34 35
18
OX9160-TQC33-A
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
156
157
158
159
160
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
138
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
45
44
43
42
41
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
63
NC
NC
NC
NC
GND
GND
GND
GND
VDD
NC
GND
GND
GND
GND
GND
VDD
NC
Mode0
Mode1
NC
EE_DI
EE_CK
GND
GND
GND
NC
NC
VDD
GND
NC
NC
NC
NC
GND
GND
GND
GND
GND
GND
NC
Figure 2: Pinout in all configurable modes (package = 160 TQFP)
Data Sheet Revision 1.1 Page 5
OX9160
OXFORD SEMICONDUCTOR LTD.
3 P
IN
D
ESCRIPTIONS
Mode
00
01
11
Dir
Name
Description
PCI Interface
139, 140, 141, 143, 144, 145,
148, 149, 152, 154, 155, 156,
159, 160, 1, 2, 14, 15, 16, 19,
20, 23, 24, 26, 28, 29, 32, 33,
34, 36, 37, 38
P_I/O
AD[31:0]
Multiplexed PCI Address/Data bus
150, 3, 13, 27
P_I
C/BE[3:0]#
PCI Command/Byte enable
136
P_I
CLK
PCI system clock
4
P_I
FRAME#
Cycle Frame
7
P_O
DEVSEL#
Device Select
5
P_I
IRDY#
Initiator ready
6
P_O
TRDY#
Target ready
9
P_O
STOP#
Target Stop request
12
P_I/O
PAR
Parity
11
P_O
SERR#
System error
10
P_I/O
PERR#
Parity error
151
P_I
IDSEL
Initialization device select
134
P_I
RST#
PCI system reset
132
P_OD
INTA #
PCI interrupt
138
P_OD
PME#
Power management event
Local bus
122
N/A
122
O
LBRST
Local bus active-high reset
123
N/A
123
O
LBRST#
Local bus active-low reset
102
O
LBDOUT
Local bus data out enable. This pin can be used by external
transceivers; it is high when LBD[7:0] are in output mode and low
when they are in input mode.
114-7
N/A
114-7
O
O
LBCS[3:0]#
LBDS[3:0]#
Local bus active-low Chip-Select (Intel mode)
Local bus active-low Data-Strobe (Motorola mode)
112
N/A
112
O
O
LBWR#
LBRDWR#
Local bus active-low write-strobe (Intel mode)
Local bus Read-not-Write control (Motorola mode)
113
N/A
113
O
Z
LBRD#
Hi-Z
Local bus active-low read-strobe (Intel mode)
Permanent high impedance (Motorola mode)
105-8
118-21
N/A
N/A
N/A
N/A
76-9,
105-8,
118-21
O
O
LBA[7:0]
LBA[12:0]
(8-bit mode) Local bus address signals
(32-bit mode) Local bus address signals
92-5
98-101
N/A
N/A
N/A
N/A
47-55,
58-61,
66-68,
80-87,
92-95,
98-101
I/O
I/O
LBD[7:0]
LBD[31:0]
(8-bit mode) Local bus data signals
(32-bit mode) Local bus data signals