Semiconductor Components Industries, LLC, 1999
December, 1999 Rev. 6
1
Publication Order Number:
SN74LS164/D
SN74LS164
Serial-In Parallel-Out
Shift Register
The SN74LS164 is a high speed 8-Bit Serial-In Parallel-Out Shift
Register. Serial data is entered through a 2-Input AND gate
synchronous with the LOW to HIGH transition of the clock. The
device features an asynchronous Master Reset which clears the
register setting all outputs LOW independent of the clock. It utilizes
the Schottky diode clamped process to achieve high speeds and is fully
compatible with all ON Semiconductor TTL products.
Typical Shift Frequency of 35 MHz
Asynchronous Master Reset
Gated Serial Data Input
Fully Synchronous Data Transfers
Input Clamp Diodes Limit High Speed Termination Effects
ESD > 3500 Volts
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
4.75
5.0
5.25
V
T
A
Operating Ambient
Temperature Range
0
25
70
C
I
OH
Output Current High
0.4
mA
I
OL
Output Current Low
8.0
mA
LOW
POWER
SCHOTTKY
Device
Package
Shipping
ORDERING INFORMATION
SN74LS164N
14 Pin DIP
2000 Units/Box
SN74LS164D
14 Pin
SOIC
D SUFFIX
CASE 751A
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 646
14
1
14
1
SN74LS164
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2
CONNECTION DIAGRAM DIP (TOP VIEW)
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Outputs
A, B
CP
MR
Q
0
Q
7
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
mA HIGH/1.6 mA LOW.
HIGH
LOW
(Note a)
LOADING
PIN NAMES
V
CC
= PIN 14
GND = PIN 7
LOGIC SYMBOL
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1
2
8
9
3
4
5
6 10 11 12 13
A
B
CP
LS164
8-BIT SHIFT REGISTER
MR Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
14
13
12
11
10
9
1
2
3
4
5
6
8
7
V
CC
Q
7
Q
6
Q
5
Q
4
MR
CP
A
B
Q
0
Q
1
Q
2
Q
3
GND
SN74LS164
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3
LOGIC DIAGRAM
Q
6
Q
7
A
B
Q
0
Q
1
Q
3
Q
2
Q
5
Q
4
MR
CP
D
Q
C
D
D
Q
C
D
D
Q
C
D
D
Q
C
D
D
Q
C
D
D
Q
C
D
D
Q
C
D
D
Q
C
D
6
3
4
5
11
12
10
13
V
CC
= PIN 14
GND = PIN 7
= PIN NUMBERS
1
2
8
9
FUNCTIONAL DESCRIPTION
The LS164 is an edge-triggered 8-bit shift register with
serial data entry and an output from each of the eight stages.
Data is entered serially through one of two inputs (A or B);
either of these inputs can be used as an active HIGH Enable
for data entry through the other input. An unused input must
be tied HIGH, or both inputs connected together.
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q
0
the logical
AND of the two data inputs (A
B) that existed before the
rising clock edge. A LOW level on the Master Reset (MR)
input overrides all other inputs and clears the register
asynchronously, forcing all Q outputs LOW.
MODE SELECT -- TRUTH TABLE
OPERATING
MODE
INPUTS
OUTPUTS
MODE
MR
A
B
Q
0
Q
1
Q
7
Reset (Clear)
L
X
X
L
L L
H
I
I
L
q
0
q
6
Shift
H
I
h
L
q
0
q
6
H
h
I
L
q
0
q
6
H
h
h
H
q
0
q
6
L (l) = LOW Voltage Levels
H (h) = HIGH Voltage Levels
X = Don't Care
q
n
= Lower case letters indicate the state of the referenced input or output one
q
n
=
set-up time prior to the LOW to HIGH clock transition.
SN74LS164
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4
DC CHARACTERISTICS OVER OPERATING
TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
V
IH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
V
IL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
V
IK
Input Clamp Diode Voltage
0.65
1.5
V
V
CC
= MIN, I
IN
= 18 mA
V
OH
Output HIGH Voltage
2.7
3.5
V
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
V
O
Output LOW Voltage
0.25
0.4
V
I
OL
= 4.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IH
or V
IL
V
OL
Output LOW Voltage
0.35
0.5
V
I
OL
= 8.0 mA
V
IN
= V
IH
or V
IL
per Truth Table
I
Input HIGH Current
20
A
V
CC
= MAX, V
IN
= 2.7 V
I
IH
Input HIGH Current
0.1
mA
V
CC
= MAX, V
IN
= 7.0 V
I
IL
Input LOW Current
0.4
mA
V
CC
= MAX, V
IN
= 0.4 V
I
OS
Short Circuit Current (Note 1)
20
100
mA
V
CC
= MAX
I
CC
Power Supply Current
27
mA
V
CC
= MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(T
A
= 25
C)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
f
MAX
Maximum Clock Frequency
25
36
MHz
t
PHL
Propagation Delay
MR to Output Q
24
36
ns
V
CC
= 5.0 V
C
L
= 15 pF
t
PLH
t
PHL
Propagation Delay
Clock to Output Q
17
21
27
32
ns
C
L
15 F
AC SETUP REQUIREMENTS
(T
A
= 25
C)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
t
W
CP, MR Pulse Width
20
ns
t
s
Data Setup Time
15
ns
V
CC
= 5 0 V
t
h
Data Hold Time
5.0
ns
V
CC
= 5.0 V
t
rec
MR to Clock Recovery Time
20
ns
SN74LS164
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5
AC WAVEFORMS
*The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock to Output Delays
and Clock Pulse Width
Figure 2. Master Reset Pulse Width,
Master Reset to Output Delay and
Master Reset to Clock Recovery Time
Figure 3. Data Setup and Hold Times
CONDITIONS: MR = H
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
t
PHL
t
PLH
CP
Q
CP
Q
MR
t
rec
t
W
t
PHL
t
W
I
/f
max
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
CP
D
Q
t
s
(H)
t
h
(H)
t
s
(L)
t
h
(L)
t
W
1/f
max
1.3 V
1.3 V
*
1.3 V
SN74LS164
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6
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 64606
ISSUE M
1
7
14
8
B
A
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.715
0.770
18.16
18.80
B
0.240
0.260
6.10
6.60
C
0.145
0.185
3.69
4.69
D
0.015
0.021
0.38
0.53
F
0.040
0.070
1.02
1.78
G
0.100 BSC
2.54 BSC
H
0.052
0.095
1.32
2.41
J
0.008
0.015
0.20
0.38
K
0.115
0.135
2.92
3.43
L
M
10
10
N
0.015
0.039
0.38
1.01
_
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
H
G
D
K
C
SEATING
PLANE
N
T
14 PL
M
0.13 (0.005)
L
M
J
0.290
0.310
7.37
7.87
SN74LS164
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7
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
A
B
G
P
7 PL
14
8
7
1
M
0.25 (0.010)
B
M
S
B
M
0.25 (0.010)
A
S
T
T
F
R
X 45
SEATING
PLANE
D
14 PL
K
C
J
M
_
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
8.55
8.75
0.337
0.344
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.054
0.068
D
0.35
0.49
0.014
0.019
F
0.40
1.25
0.016
0.049
G
1.27 BSC
0.050 BSC
J
0.19
0.25
0.008
0.009
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
5.80
6.20
0.228
0.244
R
0.25
0.50
0.010
0.019
_
_
_
_
SN74LS164
http://onsemi.com
8
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SN74LS164/D
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