Semiconductor Components Industries, LLC, 1999
December, 1999 Rev. 6
1
Publication Order Number:
SN74LS194A/D
SN74LS194A
4-Bit Bidirectional
Universal Shift Register
The SN74LS194A is a High Speed 4-Bit Bidirectional Universal
Shift Register. As a high speed multifunctional sequential building
block, it is useful in a wide variety of applications. It may be used in
serial-serial, shift left, shift right, serial-parallel, parallel-serial, and
parallel-parallel data register transfers. The LS194A is similar in
operation to the LS195A Universal Shift Register, with added features
of shift left without external connections and hold (do nothing) modes
of operation. It utilizes the Schottky diode clamped process to achieve
high speeds and is fully compatible with all ON Semiconductor TTL
families.
Typical Shift Frequency of 36 MHz
Asynchronous Master Reset
Hold (Do Nothing) Mode
Fully Synchronous Serial or Parallel Data Transfers
Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
4.75
5.0
5.25
V
T
A
Operating Ambient
Temperature Range
0
25
70
C
I
OH
Output Current High
0.4
mA
I
OL
Output Current Low
8.0
mA
LOW
POWER
SCHOTTKY
Device
Package
Shipping
ORDERING INFORMATION
SN74LS194AN
16 Pin DIP
2000 Units/Box
SN74LS194AD
16 Pin
SOIC
D SUFFIX
CASE 751B
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
SN74LS194A
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2
CONNECTION DIAGRAM DIP (TOP VIEW)
Mode Control Inputs
Parallel Data Inputs
Serial (Shift Right) Data Input
Serial (Shift Left) Data Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Parallel Outputs
S
0
, S
1
P
0
P
3
D
SR
D
SL
CP
MR
Q
0
Q
3
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
mA HIGH/1.6 mA LOW.
HIGH
LOW
(Note a)
LOADING
PIN NAMES
14
13
12
11
10
9
1
2
3
4
5
6
7
16
15
8
V
CC
MR
Q
0
Q
1
Q
2
Q
3
S
1
CP
S
0
D
SR
P
0
P
1
P
2
P
3
D
SL
GND
SN74LS194A
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3
LOGIC DIAGRAM
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
S
1
S
0
D
SR
D
SL
CP
MR
Q
0
Q
1
Q
2
Q
3
P
0
P
1
P
2
P
3
14
1
2
6
7
3
4
5
9
11
12
10
13
15
S
Q
0
CP
R
CLEAR
S
Q
1
CP
R
CLEAR
S
Q
2
CP
R
CLEAR
S
Q
3
CP
R
CLEAR
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the
functional characteristics of the LS194A 4-Bit Bidirectional
Shift Register. The LS194A is similar in operation to the
ON Semiconductor LS195A Universal Shift Register when
used in serial or parallel data register transfers. Some of the
common features of the two devices are described below:
All data and mode control inputs are edge-triggered,
responding only to the LOW to HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control and selected data inputs must be stable one set-up
time prior to the positive transition of the clock pulse.
The register is fully synchronous, with all operations
taking place in less than 15 ns (typical) making the device
especially useful for implementing very high speed CPUs,
or the memory buffer registers.
The four parallel data inputs (P
0
, P
1
, P
2
, P
3
) are D-type
inputs. When both S
0
and S
1
are HIGH, the data appearing
on P
0
, P
1
, P
2
, and P
3
inputs is transferred to the Q
0
, Q
1
, Q
2
,
and Q
3
outputs respectively following the next LOW to
HIGH transition of the clock.
The asynchronous Master Reset (MR), when LOW,
overrides all other input conditions and forces the Q outputs
LOW.
Special logic features of the LS194A design which
increase the range of application are described below:
Two mode control inputs (S
0
, S
1
) determine the
synchronous operation of the device. As shown in the Mode
Selection Table, data can be entered and shifted from left to
right (shift right, Q
0
! Q
1
, etc.) or right to left (shift left, Q
3
! Q
2
, etc.), or parallel data can be entered loading all four
bits of the register simultaneously. When both S
0
and S
1
,are
LOW, the existing data is retained in a "do nothing" mode
without restricting the HIGH to LOW clock transition.
D-type serial data inputs (D
SR
, D
SL
) are provided on both
the first and last stages to allow multistage shift right or shift
left data transfers without interfering with parallel load
operation.
SN74LS194A
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4
MODE SELECT -- TRUTH TABLE
OPERATING MODE
INPUTS
OUTPUTS
OPERATING MODE
MR
S
1
S
0
D
SR
D
SL
P
n
Q
0
Q
1
Q
2
Q
3
Reset
L
X
X
X
X
X
L
L
L
L
Hold
H
I
I
X
X
X
q
0
q
1
q
2
q
3
Shift Left
H
h
I
X
I
X
q
1
q
2
q
3
L
H
h
I
X
h
X
q
1
q
2
q
3
H
Shift Right
H
I
h
I
X
X
L
q
0
q
1
q
2
H
I
h
h
X
X
H
q
0
q
1
q
2
Parallel Load
H
h
h
X
X
P
n
P
0
P
1
P
2
P
3
L = LOW Voltage Level
H = HIGH Voltage Level
X = Don't Care
I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition
h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition
p
n
(q
n
) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
V
IH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
V
IL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
V
IK
Input Clamp Diode Voltage
0.65
1.5
V
V
CC
= MIN, I
IN
= 18 mA
V
OH
Output HIGH Voltage
2.7
3.5
V
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
V
O
Output LOW Voltage
0.25
0.4
V
I
OL
= 4.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IL
or V
IH
V
OL
Output LOW Voltage
0.35
0.5
V
I
OL
= 8.0 mA
V
IN
= V
IL
or V
IH
per Truth Table
I
Input HIGH Current
20
A
V
CC
= MAX, V
IN
= 2.7 V
I
IH
Input HIGH Current
0.1
mA
V
CC
= MAX, V
IN
= 7.0 V
I
IL
Input LOW Current
0.4
mA
V
CC
= MAX, V
IN
= 0.4 V
I
OS
Short Circuit Current (Note 1)
20
100
mA
V
CC
= MAX
I
CC
Power Supply Current
23
mA
V
CC
= MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(T
A
= 25
C)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
f
MAX
Maximum Clock Frequency
25
36
MHz
t
PLH
t
PHL
Propagation Delay,
Clock to Output
14
17
22
26
ns
V
CC
= 5.0 V
C
L
= 15 pF
t
PHL
Propagation Delay,
MR to Output
19
30
ns
C
L
15 F
SN74LS194A
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5
AC SETUP REQUIREMENTS
(T
A
= 25
C)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
t
W
Clock or MR Pulse Width
20
ns
t
s
Mode Control Setup Time
30
ns
t
s
Data Setup Time
20
ns
V
CC
= 5.0 V
t
h
Hold time, Any Input
0
ns
t
rec
Recovery Time
25
ns
DEFINITIONS OF TERMS
SETUP TIME(t
s
) --is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (t
h
) -- is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (t
rec
) -- is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock to Output Delays Clock Pulse
Width and f
max
Figure 2. Master Reset Pulse Width, Master Reset
to Output Delay and Master Reset to Clock
Recovery Time
1.3 V
1.3 V
OTHER CONDITIONS: S
1
= L, MR = H, S
0
= H
OTHER CONDITIONS: S
0
, S
1
= H
OTHER CONDITIONS:
P
O
= P
1
= P
2
= P
3
= H
OTHER CONDITIONS: MR = H
OTHER CONDITIONS:
*D
SR
SET-UP TIME AFFECTS Q
0
ONLY
OTHER CONDITIONS:
D
SL
SET-UP TIME AFFECTS Q
3
ONLY
OTHER CONDITIONS: MR = H
S
0
S
1
D
SR
D
SL
P
0
P
1
P
2
P
3
CLOCK
OUTPUT*
( IS SHIFT LEFT)
CLOCK
CLOCK
CLOCK
OUTPUT
OUTPUT
S
0
S
1
t
s
(H)
t
h
(L) = 0
t
h
(H) = 0
t
h
(H) = 0
t
s
(H)
t
h
(L) = 0
t
s
(L)
t
h
= 0
t
h
= 0
(STABLE TIME)
t
PHL
t
PLH
1/fmax
t
W
t
s
(L)
MR
t
W
t
rec
t
PHL
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
t
s
t
s
Figure 3. Setup (t
s
) and Hold (t
h
) Time for Serial Data
(D
SR
, D
SL
) and Parallel Data (P
0
, P
1
, P
2
, P
3
)
Figure 4. Setup (t
s
) and Hold (t
h
) Time for S Input
SN74LS194A
http://onsemi.com
6
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 64808
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
A
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1
8
9
16
K
PLANE
T
M
A
M
0.25 (0.010)
T
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.740
0.770
18.80
19.55
B
0.250
0.270
6.35
6.85
C
0.145
0.175
3.69
4.44
D
0.015
0.021
0.39
0.53
F
0.040
0.70
1.02
1.77
G
0.100 BSC
2.54 BSC
H
0.050 BSC
1.27 BSC
J
0.008
0.015
0.21
0.38
K
0.110
0.130
2.80
3.30
L
0.295
0.305
7.50
7.74
M
0
10
0
10
S
0.020
0.040
0.51
1.01
_
_
_
_
SN74LS194A
http://onsemi.com
7
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
8
16
9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PL
P
B
A
M
0.25 (0.010)
B
S
T
D
K
C
16 PL
S
B
M
0.25 (0.010)
A
S
T
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
9.80
10.00
0.386
0.393
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.054
0.068
D
0.35
0.49
0.014
0.019
F
0.40
1.25
0.016
0.049
G
1.27 BSC
0.050 BSC
J
0.19
0.25
0.008
0.009
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
5.80
6.20
0.229
0.244
R
0.25
0.50
0.010
0.019
_
_
_
_
SN74LS194A
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8
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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
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SN74LS194A/D
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