Semiconductor Components Industries, LLC, 2001

October, 2001 Rev. 6

Publication Order Number:

CS5305/D

CS5305

Three-Phase Synchronous

Switching Step-Down

Controller with Single

Wire Current Sharing

The CS5305 provides a lowcost, singlecontroller solution for the

lowvoltage, highcurrent power needs of nextgeneration
workstation and server processors. This IC provides high accuracy and
the industry's fastest transient response, reducing the need for large
banks of output capacitors and providing the most compact, reliable,
and economical power supply.

Since each phase's output voltage and current feed back to develop

the PWM ramp signal (enhanced V

control), the CS5305 shares

output current accurately between phases. Accurate current sharing
means that the power supply design does not need to use power
components rated to handle mismatched current per phase. The
enhanced V

control compensates for variations in both line and load.

The IC's builtin single wire current sharing capability allows easy

paralleling of multiple Voltage Regulator Modules (VRMs) based on
the CS5305. The paralleled VRMs use a shared bus to provide high
current and high reliability to multiple microprocessor workstations
or servers.

The CS5305 meets VRM 9.x specifications with its Power Good,

Enable, Differential Remote Sense, and singlewire Current Share
features. The product fits server and workstation VRMs, and can be
used to power Embedded Processors. The IC provides the simplest,
lowestcost solution for any low voltage, high current power supply.

Features

Enhanced V

Control Method

VRM 9.x Compatible VID Codes

Lossless Inductor Current Sensing

Single Wire Active Current Sharing Between Converters

Auto MasterSlave Current Share Control Method

Programmable 200 to 800 kHz Switching Frequency

Programmable Adaptive Voltage Positioning

Differential Remote Sense

PulsebyPulse Current Limit

Master Hiccup Overcurrent Protection through Single

Wire Share Bus

5Bit DAC with 1% Tolerance

ENABL Input

VRM 9.xCompliant Power Good Output

Active Current Sharing During Soft Start

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Device

Package

Shipping

ORDERING INFORMATION

SO28L

27 Units/Rail

SO28L

1000 Tape & Reel

SO28L

DW SUFFIX

CASE 751F

PWRGDS

SGND

REF

CS3

DRVON

CS2

GATE3

CS1

GATE2

ENABL

GATE1

OSC

GND

OCSET

ID0

OUT

ID1

ID3

DRP

ID2

SCOMP

ID4

PWRGD

COMP

PIN CONNECTIONS

CS5305GDW28

CS5305GDWR28

MARKING

DIAGRAMS

= Assembly Location

WL, L

= Wafer Lot

YY, Y

= Year

WW, W = Work Week

CS5305

AWLYYWW

CS5305

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APPLICATION DIAGRAMS

GND

GATE1

GATE2

GATE3

DRVON

SGND

PWRGDS

ID0

ID1

ID2

ID3

ID4

PWRGD

OCSET

OSC

ENABL

CS1

CS2

CS3

REF

OUT

SCOMP

DRP

COMP

CS5305

3.9 k

47 nF

12 k

3 k

.01

22 nF

91 k

17 k

220

0.1

220

12 k

47 nF

GND SENSE

POWERGOOD

OUT

SENSE

ID4

ID3

ID2

ID1

ID0

60.4 k

NCP5351

ENABLE

PGND

BST

SWN

.47 nF

NTD
4302

NTD

4302

BAS40LT1

NCP5351

ENABLE

PGND

BST

SWN

NTD
4302

BAS40LT1

NCP5351

ENABLE

PGND

BST

SWN

NTD
4302

BAS40LT1

NTD
4302

OUT

100

270 nH

470 nH

20 k

ENABLE

28.7 k

+12 V

2.2

220 k

0.1

6.2 V

GND

5.6 V

.47

Figure 1. VRM 9.0, 60 A Converter

CS5305

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12 V

ENABLE
V

ID0

ID1

ID2

ID3

ID4

OUT

SENSE

OUT

GND

GND SENSE

POWERGOOD

12 V

ENABLE
V

ID0

ID1

ID2

ID3

ID4

OUT

SENSE

OUT

GND

GND SENSE

POWERGOOD

ENABLE

ID0

ID1

ID2

ID3

ID4

12 V

5.0 V

GND

OUT

POWERGOOD

1.5 k

Inductors & Resistors
represent distribution
impedances.

Figure 2. TwoConverter System with Sharing

MAXIMUM RATINGS*

Rating

Value

Unit

Operating Junction Temperature

150

Storage Temperature Range

65 to 150

ESD Susceptibility (Human Body Model)

2.0

Thermal Resistance, JunctiontoCase, R

C/W

Thermal Resistance, JunctiontoAmbient, R

C/W

JEDEC Moisture Sensitivity

Level 5

Lead Temperature Soldering:

Reflow: (SMD styles only) Note 1.

230 peak

1. 60 second maximum above 183

*The maximum package power dissipation must be observed.

MAXIMUM RATINGS

Pin Number

Pin Symbol

MAX

MIN

SOURCE

SINK

OCSET

7.0 V

0.3 V

1.0 mA

OSC

7.0 V

0.3 V

1.0 mA

ENABL

16 V

0.3 V

1.0 mA

CS13

7.0 V

0.3 V

1.0 mA

REF

7.0 V

0.3 V

1.0 mA

7.0 V

0.3 V

1.0 mA

OUT

7.0 V

0.3 V

10 mA

16 V

0.3 V

50 mA

1.0 mA

SCOMP

7.0 V

0.3 V

1.0 mA

DRP

7.0 V

0.3 V

1.0 mA

7.0 V

0.3 V

1.0 mA

COMP

7.0 V

0.3 V

10 mA

1.0 mA

PWRGD

16 V

0.3 V

1.0 mA

20 mA

CS5305

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MAXIMUM RATINGS (continued)

Pin Number

SINK

SOURCE

MIN

MAX

Pin Symbol

1620

ID4

ID0

16 V

0.3 V

1.0 mA

PWRGDS

7.0 V

0.3 V

1.0 mA

SGND

0.3 V

1.0 mA

16 V

0.3 V

N/A

0.4 A, 1.0

s 100 mA DC

DRVON

7.0 V

0.3 V

10 mA

1.0 mA

2527

GATE 31

16 V

0.3 V

0.1 A, 1.0

s; 25 mA DC

0.1 A, 1.0

s 25 mA DC

GND

N/A

0.4 A, 1.0

s; 100 mA DC

N/A

ELECTRICAL CHARACTERISTICS

C < T

< 70

C; 0

C < T

< 125

C; 9.5 V < V

< 14 V; C

GATEX

= 100 pF,

COMP

= 0.01

F, C

SCOMP

= 0.01

F, C

VCC

= 0.1

F, R

ROSC

= 32.4 k

, R

= 60.4 k

, V(OCSET) = 0.54 V, DAC Code 01110; unless

otherwise stated.)

Parameter

Test Conditions

Min

Typ

Max

Unit

Voltage Identification DAC (0 = Connected to GND, 1 = Open (Pulledup to internal 3.3 V) or Pulledup to external voltage

13 V)

Accuracy (all codes)

VID code 125 mV

Connect VFB to COMP,

SGND < 55 mV,

Measure COMP SGND

1.0

ID4

ID3

ID2

ID1

ID0

Maximum Voltage

DRVON < 1.0 V, GATE

< 1.0 V

FAULT Mode

1.100

0.965

0.975

0.985

1.125

0.990

1.000

1.010

1.150

1.015

1.025

1.035

1.175

1.040

1.050

1.061

1.200

1.064

1.075

1.086

1.225

1.089

1.100

1.111

1.250

1.114

1.125

1.136

1.275

1.139

1.150

1.162

1.300

1.163

1.175

1.187

1.325

1.188

1.200

1.212

1.350

1.213

1.225

1.237

1.375

1.238

1.250

1.263

1.400

1.263

1.275

1.288

1.425

1.287

1.300

1.313

1.450

1.312

1.325

1.338

1.475

1.337

1.350

1.364

1.500

1.361

1.375

1.389

1.525

1.386

1.400

1.414

1.550

1.411

1.425

1.439

1.575

1.436

1.450

1.465

1.600

1.460

1.475

1.490

1.625

1.485

1.500

1.515

1.650

1.510

1.525

1.540

CS5305

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ELECTRICAL CHARACTERISTICS (continued)

C < T

< 70

C; 0

C < T

< 125

C; 9.5 V < V

< 14 V; C

GATEX

= 100 pF,

COMP

= 0.01

F, C

SCOMP

= 0.01

F, C

VCC

= 0.1

F, R

ROSC

= 32.4 k

, R

= 60.4 k

, V(OCSET) = 0.54 V, DAC Code 01110; unless

otherwise stated.)

Parameter

Unit

Max

Typ

Min

Test Conditions

Voltage Identification DAC (0 = Connected to GND, 1 = Open (Pulledup to internal 3.3 V) or Pulledup to external voltage

13 V)

1.675

1.535

1.550

1.566

1.700

1.560

1.575

1.591

1.725

1.584

1.600

1.616

1.750

1.609

1.625

1.641

1.775

1.634

1.650

1.667

1.800

1.658

1.675

1.692

1.825

1.683

1.700

1.717

1.850

1.708

1.725

1.742

Input Threshold

ID4

, V

ID3

, V

ID2

, V

ID1

, V

ID0

1.00

1.25

1.5

Input Pullup Resistance

0 V < V

ID4

, V

ID3

, V

ID2

ID1

ID0

< 3.3 V

100

Pullup Voltage

1.0 M

to GND

2.5

2.7

3.0

SGND Bias Current

SGND < 55 mV, All DAC Codes

Power Good Output

Upper Threshold

Force PWRGDSSGND

SGND < 55 mV

1.876 (5%)

1.975

2.074 (+5%)

Lower Threshold

Force PWRGDSSGND

SGND < 55 mV

0.95

125 mV)

or 2.6% from

nominal PWRGD

Threshold

0.975

125 mV)

125 mV

or +2.6% from

nominal

PWRGD

Threshold

ID4

ID3

ID2

ID1

ID0

0.926

0.951

0.975

0.950

0.975

1.000

0.974

1.000

1.025

0.998

1.024

1.050

1.021

1.048

1.075

1.045

1.073

1.100

1.069

1.097

1.125

1.093

1.122

1.150

1.116

1.146

1.175

1.140

1.170

1.200

1.164

1.195

1.225

1.188

1.219

1.250

1.211

1.243

1.275

1.235

1.268

1.300

1.259

1.292

1.325

1.283

1.316

1.350

1.306

1.341

1.375

CS5305

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ELECTRICAL CHARACTERISTICS (continued)

C < T

< 70

C; 0

C < T

< 125

C; 9.5 V < V

< 14 V; C

GATEX

= 100 pF,

COMP

= 0.01

F, C

SCOMP

= 0.01

F, C

VCC

= 0.1

F, R

ROSC

= 32.4 k

, R

= 60.4 k

, V(OCSET) = 0.54 V, DAC Code 01110; unless

otherwise stated.)

Parameter

Unit

Max

Typ

Min

Test Conditions

Power Good Output

1.330

1.365

1.400

1.354

1.389

1.425

1.378

1.414

1.450

1.401

1.438

1.475

1.425

1.463

1.500

1.449

1.487

1.525

1.473

1.511

1.550

1.496

1.536

1.575

1.520

1.560

1.600

1.544

1.584

1.625

1.568

1.609

1.650

1.591

1.633

1.675

1.615

1.658

1.700

1.639

1.682

1.725

Switch Leakage Current

= 14 V, PWRGDS = 1.4 V

1.0

Delay

PWRGDS low to PWRGD low

250

600

Output Low Voltage

PWRGDS = 1.0 V,

PWRGOOD

= 4.0 mA

0.15

0.4

Voltage Feedback Error Amplifier

Bias Current

Note 2.

9.5

10.3

11.5

Comp Source Current

COMP = 0.5 V to 2.0 V,

= 1.6 V

Comp Sink Current

COMP = 0.5 V to 2.0 V,

= 1.0 V

Transconductance

A < I

COMP

< +10

A, Note 3.

32.0

mmho

Output Impedance

Note 3.

2.5

Open Loop DC Gain

Note 3.

Unity Gain Bandwidth

COMP = 0.01

F, Note 3.

kHZ

PSRR @ 1.0 kHz

Note 3.

COMP Max Voltage

= 0 V

2.4

2.7

COMP Min Voltage

= 1.6 V

0.1

0.2

COMP Discharge Threshold

0.15

0.2

0.25

Hiccup Latch Discharge Current

CSx CS

REF

= .05 V,

OCSET = 0.1 V,
COMP = 0.5 V

2.0

5.0

Hiccup Charge / Discharge Ratio

4.5

6.0

7.5

2. The V

Bias Current changes with the value of R

OSC

per Figure 5.

3. Guaranteed by design. Not tested in production.

CS5305

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ELECTRICAL CHARACTERISTICS (continued)

C < T

< 70

C; 0

C < T

< 125

C; 9.5 V < V

< 14 V; C

GATEX

= 100 pF,

COMP

= 0.01

F, C

SCOMP

= 0.01

F, C

VCC

= 0.1

F, R

ROSC

= 32.4 k

, R

= 60.4 k

, V(OCSET) = 0.54 V, DAC Code 01110; unless

otherwise stated.)

Parameter

Unit

Max

Typ

Min

Test Conditions

Voltage Feedback Error Amplifier

SHARE Fault Discharge Current

SHARE = 3.5 V,

COMP = 0.5 V,
CSx = CS

REF

= 0 V,

OCSET = 0.5 V

0.3

2.5

5.0

Enable Input

Threshold Voltage

Monitor DRVON

1.12

1.25

1.38

Pullup Voltage

1 M

to GND

2.5

2.7

3.0

Input Pullup Resistance

100

PWM Comparators

Minimum Pulse Width

Measured from CSx to GATEx,

= CS

REF

= 0.5 V,

COMP = 0.5 V,
60 mV step on CSx;
measure at GATEx = 1.0 V

220

Transient Response Time

Measured from CS

REF

to GATEx,

COMP = 2.1 V,
CSx = CS

REF

= 0.5 V,

REF

stepped

from 1.2 V 2.0 V

100

150

Channel Startup Offset

CSx = CS

REF

= V

= 0 V,

measure V(COMP) when
GATEx switch high

0.34

0.6

0.75

Channel Startup Offset

Mismatch

CSx = CS

REF

= V

= 0 V,

measure V(COMP) when
GATEx switch high, Note 4.

5.0

Gates

High Voltage

GATEx

= 1.0 mA

2.25

2.5

3.0

Low Voltage

GATEx

= 1.0 mA

0.2

0.4

Rise Time GATE

0.8 V < GATE < 2.0 V,

= 10 V

Fall Time GATE

2.0 V > GATE > 0.8 V,

= 10 V

Oscillator

Switching Frequency

OSC

= 32.4 k

300

400

500

kHz

Switching Frequency

OSC

= 63.4 k

Note 4.

150

200

250

kHz

Switching Frequency

OSC

= 16.2 k

Note 4.

600

800

1000

kHz

OSC

Voltage

Note 4.

0.90

1.00

1.10

Phase Delay

120

150

deg

4. Guaranteed by design. Not tested in production.

CS5305

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ELECTRICAL CHARACTERISTICS (continued)

C < T

< 70

C; 0

C < T

< 125

C; 9.5 V < V

< 14 V; C

GATEX

= 100 pF,

COMP

= 0.01

F, C

SCOMP

= 0.01

F, C

VCC

= 0.1

F, R

ROSC

= 32.4 k

, R

= 60.4 k

, V(OCSET) = 0.54 V, DAC Code 01110; unless

otherwise stated.)

Parameter

Unit

Max

Typ

Min

Test Conditions

Current Sense Amplifiers

REF

Input Bias Current

REF

= CSx = 0 V

0.3

3.0

CSx Input Bias Current

REF

= CSx = 0 V

0.1

1.0

Sense Amp Gain

REF

= 0 V, CSx = 0.05 V,

Measure V(COMP) when
GATEx switches high

.95

1.06

1.17

V / V

Mismatch

(CSx CS

REF

)

50 mV,

Note 5.

3.0

Common Mode Input Range

Note 5.

2.0

Bandwidth

Note 5.

7.0

MHz

Single Phase Pulse by Pulse

Current Limit

= CS

REF

= 0.5 V,

COMP = 2.0 V, Measure
CSx CS

REF

when GATEx

goes low

100

OCSET Input Bias Current

OCSET = 0 V

0.1

1.0

Current Sense Input to OCSET

Gain

OCSET / R (CSx CS

REF

OCSET = 0.6 V,
Monitor DRVON < 1.0 V

3.4

3.7

4.0

V / V

Current Limit Filter Slew Rate

REF

= 1.1 V, CSx = 1.0 V,

pulse CSx to 1.16 V, Note 5.

2.0

5.0

mV /

Adaptive Voltage Positioning

DRP

Output Voltage to

DAC

OUT

Offset

CSx = CS

REF

, V

= COMP,

Measure V

DRP

COMP

2.0

Maximum V

DRP

Voltage

CSx CS

REF

= 50 mV,

= COMP,

Measure V

DRP

COMP

500

560

620

Current Sense Amp to V

DRP

Gain

CSx CS

REF

= 50 mV,

= COMP,

Measure V

DRP

COMP

3.4

3.7

4.0

V / V

DRP

Source Current

CSx CS

REF

= 50 mV,

= COMP,

DRP

= 1.5 V

1.0

7.0

SHARE Current Sense Amplifier

Input Bias Current

= 0 V

0.2

1.0

Input Offset Voltage

Note 5.

5.0

Common Mode Input Range

Note 5.

2.0

Output Current

OUT

= 0 V, CSx = 0.667 V,

REF

= 0.5 V

1.0

Gain

Note 5.

120

Output Unity Gain BW

Note 5.

5.0

MHz

5. Guaranteed by design. Not tested in production.

CS5305

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ELECTRICAL CHARACTERISTICS (continued)

C < T

< 70

C; 0

C < T

< 125

C; 9.5 V < V

< 14 V; C

GATEX

= 100 pF,

COMP

= 0.01

F, C

SCOMP

= 0.01

F, C

VCC

= 0.1

F, R

ROSC

= 32.4 k

, R

= 60.4 k

, V(OCSET) = 0.54 V, DAC Code 01110; unless

otherwise stated.)

Parameter

Unit

Max

Typ

Min

Test Conditions

SHARE Bus

SHARE Amplifier Offset Voltage

Measure V(SHARE) V(I

OUT

0 < I

OUT

< 2.0 V

SHARE Amplifier Source

Current

OUT

= 2.1 V, SHARE = 2.0 V

1.0

7.5

SHARE Amplifier Max Voltage

OUT

= 3.5 V, T

= 25

2.65

2.80

3.20

SHARE Fault Threshold

DRVON < 1.0 V, T

= 25

3.2

3.4

3.7

SHARE OK Threshold

DRVON > 1.0 V

2.0

2.3

2.5

SHARE Fault Hysteresis

1.0

1.15

1.3

SHARE Fault Output Voltage

3.8

4.25

4.7

SHARE Fault Output Current

SHARE = 3.8 V

1.2

2.0

2.5

SHARE Full Load Accuracy

REF

= 0.5 V, CSx = 0.52 V,

OUT

/ FB Divider = 22 k

/3.0 k

1.7

1.95

2.2

SHARE Short Circuit Current

V(I

OUT

) = 2.0 V, SHARE = GND

1.0

SHARE Fault Short Circuit

Current

REF

= 0.5 V, CSx = 0.6 V

2.0

Current SHARE Adjust Amplifier

Transconductance from I

OUT

SCOMP

0 < I

OUT

< 2.0 V,

0 < SCOMP < 2.0 V

A / V

Gain from I

OUT

to COMP

Note 6.

140

mA / V

Maximum SCOMP source

current

SCOMP = 1.5 V

Maximum SCOMP sink current

SCOMP = 1.5 V

Unity Gain BW

C(SCOMP) = TBD, Note 6.

100

MOSFET Driver Enable

PullUp Voltage

DRVON Floating

4.5

5.5

6.0

DRVON Source Current

DRVON = 1.5 V

3.0

6.5

DRVON Pull Down Resistor

DRVON = 1.5 V, ENABL = 0 V,

R = 1.5 V / I(1.5 V)

140

General Electrical Specifications

Disable Current

ENABLE = 0 V (no switching)

UVLO Start Threshold

COMP charging, DRVON > 1.0 V

8.5

9.0

9.5

UVLO Stop Threshold

Gates not switching, COMP

discharging, DRVON < 1.0 V

7.5

8.0

8.5

UVLO Hysteresis

Start Stop

0.8

1.0

1.2

Operating Current

ENABLE Open

6. Guaranteed by design. Not tested in production.

CS5305

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PACKAGE PIN DESCRIPTION

Package Pin Number

SO28L

Pin Symbol

Pin Name

Function

OCSET

OverCurrent Set

Resistor divider from R

OSC

to GND programs the threshold of the hiccup

overcurrent protection.

OSC

Oscillator Frequency

Adjust

Resistance to GND programs the oscillator frequency. It also programs the V

bias current shown in Figure 5.

ENABL

Enable Input

TTLCompatible logic input with 50 k

internal pullup resistor to 3.3 V. A logic

low puts the IC in FAULT mode.

CS13

Current Sense Inputs

Noninverting inputs to the current sense amplifiers.

REF

Current Sense

Reference

Inverting input to the current sense amplifiers, and fast feedback input to the
PWM comparator.

Share Current Amp

Inverting Input

Inverting input to share current amp. Connect resistor divider between I

OUT

, I

and IC GND pin 28 to program Share Current Amp gain.

OUT

Share Current Amp

Output

Share current amplifier output and input to share adjust amplifier.

Share Bus

Connect with other modules for singlewire current sharing.

SCOMP

Share Compensation

Connect compensation network to stabilize share loop.

DRP

Current Sense Output

for AVP

The offset of this pin above the DAC voltage is proportional to the output current.
Connect a resistor from this pin to V

to program the AVP voltage or leave this

pin open for no AVP.

Voltage Feedback

Error Amp inverting input. Input bias current used to program AVP light load
offset via resistor connected to converter output voltage. Short V

to the

converter output voltage for no AVP.

COMP

Error Amp Output and

PWM Comparator

Input

Provides loop compensation. Also used to control Softstart and Fault timing.

PWRGD

Power Good Output

Open collector output goes low when V

is out of regulation. User must

externally limit current into this pin to less than 20 mA.

1620

ID4

ID0

Voltage ID DAC

Inputs

Programs Output Voltage. 50 k

internal pullup resistors to 3.3 V.

PWRGDS

Power Good Sense

Provides remote output voltage sensing.

SGND

Reference Ground

Ground connection for the DAC. Provides remote sensing of ground at the load.

Supply Input

IC Power Supply Input.

DRVON

Driver Enable

Logic High enables outputs of compatible MOSFET Driver ICs. Low turns all
MOSFETs OFF. Pin driven from internal 5.5 V; 70 k

internal resistor to GND.

2527

GATE 31

FET Driver Outputs

PWM Signal Input to external MOSFET Gate Driver ICs.

GND

Ground

IC Power Supply Return; connected to IC substrate.

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ID0

ID1

ID2

ID3

ID4

DAC

SGND

3.3 V

OCSET

DAC OUTPUT

VID = 1

1111

OC Filter

- +

1.25 V

ENABL

ENABLE

Comparator

50 k

3.3 V

Start

Stop

9.0 V

8.0 V

UVLO

Comparator

- +

0.2 V

Discharge

Comparator

Reset

Dominant

Fault

* 0.975 V

- +

DRP

COMP

Reset

- +

PWM1

Comparator

ILIM1

Comparator

0.33

CO1

CO1F

- +

PWM2

Comparator

ILIM2

Comparator

0.33 V

CO2

CO2F

- +

PWM3

Comparator

ILIM3

Comparator

0.33 V

CO3

CO3F

Reset

Dominant

Reset

Dominant

Reset

Dominant

PGND

TE2

TE1

TE3

Latch

PWM1

Latch

PWM2

Latch

PWM3

VP Amp

Delay

1.975 V

PWRGDS

PWRGD

3.7

CO1

CO1F

3.7

CO2

CO2F

3.7

CO3

CO3F

- +

REF

CS1

CS2

CS3

SHARE Current Sense

Amp

30 mV

OUT

SHARE Bus Amp

Adjust Amp

SCOMP

Start

Stop

3.1 V

2.1 V

SHARE Fault

Comparator

Error Amp

F
AUL

0.6 V

3.3 V

3.8 V

Fault

IBIAS

IDISCHG

AUL

COMP

Current Source

Generator

1.0 V

PULSEOUT1

PULSEOUT2

PULSEOUT3

IOSC

OSCILLA

GND

AUL

5.5 V

VON

70 k

Comparator

Figure 3. Block Diagram

PGND

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. Oscillator Frequency

(mA)

Temperature (

100

125

ENABL = Low

ENABL = Floating
Gates Switching

Threshold V

oltage (V)

8.0

Temperature (

8.2

8.4

8.6

8.8

9.0

9.2

9.4

100

125

Start Threshold

Stop Threshold

Oscillator Frequency (kHz)

400

Temperature (

405

410

100

125

DAC Output (V)

1.348

Temperature (

1.349

1.350

1.351

1.352

1.353

1.354

100

125

Frequency (kHz)

100

OSC

Value (k

)

300

400

500

600

700

800

900

200

Bias Current (

OSC

Value

Figure 5. V

Bias Current vs. R

OSC

Value

Figure 6. I

vs. Temperature

Figure 7. UVLO Start and Stop Thresholds vs.

Temperature

Figure 8. Oscillator Frequency vs. Temperature for

OSC

= 32.4 k

Figure 9. DAC Output for VID = 01111 (1.475 V)

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 10. DAC Output for VID = 00110 (1.700 V)

Figure 11. GATE Phase Delay vs. Temperature

Figure 12. GATE Rise and Fall Time vs. Temperature

Figure 13. PWM Comparator Minimum Pulse

Width vs. Temperature

Figure 14. PWM Transient Response Time vs.

Temperature

Figure 15. Current Sense Amp Channel StartUp

Offset Voltage vs. Temperature

DAC Output (V)

1.572

Temperature (

1.574

1.576

1.578

1.580

1.582

100

125

Phase Delay (degrees)

100

Temperature (

110

115

120

125

130

135

140

100

125

105

GATE3 to GATE1

GATE2 to GATE3

GATE1 to GATE2

Rise/Fall T

imes (ns)

4.0

Temperature (

6.0

8.0

100

125

Rise Time

Fall Time

Minimum Pulse Width (ns)

Temperature (

100

125

ransient Response T

ime (ns)

Temperature (

100

120

140

160

100

125

StartUp Of

fset V

oltage (mV)

400

Temperature (

450

500

550

600

650

700

100

125

LOAD

= 100 pF

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 16. Current Sense Amplifier Gain vs.

Temperature

Figure 17. V

Bias Current vs. Temperature for

OSC

= 32.4 k

Figure 18. V

DRP

Source Current vs. Temperature

Figure 19. V

DRP

to DAC Output Offset Voltage vs.

Temperature

Figure 20. SHARE Bus Voltages vs. Temperature

Figure 21. I

OUT

Output Current vs. Temperature

Current

Sense Gain (V/V)

1.0

Temperature (

1.5

2.0

2.5

3.0

3.5

4.0

100

125

Current Sense Amp to V

DRP

Gain

Current Sense Amp to OSCETGain

Current Sense Amp to PWM Comparator Gain

Bias Current (

10.55

Temperature (

10.60

10.65

10.70

10.75

10.80

10.85

10.90

100

125

V(V

) = 1.9 V

V(V

) = 1.0 V

DRP

Source Current (mA)

6.0

Temperature (

6.5

7.0

7.5

8.0

8.5

100

125

DRP

to DAC Output Of

fset V

oltage (mV)

0.8

Temperature (

1.0

1.2

1.4

1.6

100

125

SHARE Bus V

oltages (V)

1.5

Temperature (

2.0

2.5

3.0

3.5

4.0

4.5

100

125

SHARE Fault Output Voltage

SHARE Fault Threshold

SHARE Max Output Voltage

SHARE OK Threshold

SHARE Full Load Accuracy

OUT

Output Current (mA)

13.0

Temperature (

13.5

14.0

14.5

15.0

15.5

16.0

100

125

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 22. SHARE Offset Voltage vs. Temperature

Figure 23. I

OUT

to S

COMP

Transconductance vs.

Temperature

Figure 24. Power Good Lower Threshold Voltage vs.

Temperature

Figure 25. Power Good Upper Threshold Voltage vs.

Temperature

Figure 26. Power Good Delay vs. Temperature

SHARE Of

fset V

oltage (mV)

Temperature (

100

125

OUT

to S

COMP

ransconductance (

A/V)

Temperature (

100

125

Percentage Change Over Nominal (%)

0.06

Temperature (

0.04

0.02

0.04

0.06

100

125

VID = 11110

VID = 01110

VID = 00000

Power Good Upper Threshold V

oltage (V)

1.975

Temperature (

1.985

1.990

1.995

2.000

2.005

2.010

2.015

100

125

1.980

Power Good Delay (

210

Temperature (

215

220

225

230

235

100

125

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APPLICATIONS INFORMATION

THEORY OF OPERATION

Fixed Frequency Multiphase Control

Multiphase CPU controllers include the necessary control

circuitry to implement several buck converters in parallel.
These converters are configured to turn on at different times.
This allows much higher output current than could be
provided by a single converter. The apparent ripple frequency
is increased and so output current can ramp up or down faster
than a single converter with the same value of output
inductor. Heat is also spread among multiple components.

The CS5305 uses a fixed frequency, Enhanced V

architecture. Each phase is delayed by approximately 120

from the previous phase. The GATE output for each channel
changes to a logic high at the beginning of its oscillator cycle.
Inductor current ramps up until the combination of the current
sense signal and the output ripple trip the PWM comparator,
at which time the GATE output changes to a logic low. Once
low, the GATE output remains low until the next oscillator
cycle begins, and the control loop will not respond until that
time. The Enhanced V

control loop will respond to line and

load transients while the GATE output is high. Enhanced V

control will respond within the off time of the converter.

PWM
COMP

OFFSET

CS AMP

ERROR
AMP

CSx

REF

COMP

CSx

COMP

ESR

SWITCH

OUT

NODE

Figure 27.

The Enhanced V

architecture measures and adjusts

current in each phase. An additional input (CSx pin)
provides current information for each output phase to the
control loop as shown in Figure 27. Inductor current is
measured across capacitor Ccsx. The voltage across this
capacitor is equal to the product of the output current and the
inductor ESR if these components are chosen such that
(Ccsx)(Rcsx) = (L)/ESR

. This signal is buffered by the

current sense amplifier (unity gain in the CS5305) and
summed with an offset voltage before it is presented as input
to noninverting input of the PWM comparator. Inductor
current provides the PWM ramp. As inductor current

increases, the voltage at the positive input to the PWM
comparator rises and terminates the PWM cycle. If the
inductor starts the next cycle with higher current, the PWM
cycle terminates earlier, thus providing negative feedback.
A CSx input is provided for each channel, but the CS

REF

and COMP inputs are common to all phases. Current

sharing between phases is accomplished by referencing all
phases to the same error amplifier. Any phase with a larger
current signal will turn off earlier than the channels with a
lower current signal.

Including both current and voltage information in the

feedback signal allows the open loop output impedance of the
power stage to be controlled. In the absence of any load
current, the COMP pin voltage will be equal to the sum of the
output voltage, the offset voltage and half of the steadystate
ramp voltage. (At no load, the output ripple current's positive
and negative contributions are equal, and the DC averaged
voltage is equal to half the ripple voltage.) If the COMP pin
is held steady and the inductor current is forced to change, the
output voltage will also change. In a closedloop situation,
changing the inductor current will force the COMP voltage to
change so the output voltage can remain the same. The change
in COMP voltage depends on the scaling of the current
feedback signal, and can be defined as:

VCOMP

(ESRL)(Current Sense Gain)(

IPHASE)

Since the current sense gain for this loop is unity, this

equation reduces to:

VCOMP

(ESRL)(

IPHASE)

and so the singlephase power stage output impedance is:

VCOMP

IPHASE

ESRL

The CS5305 has three phases, so the total power stage

output impedance is then ESR

/3.

Lossless Inductive Current Sensing

Current can be sensed across the inductor as shown in

Figure 27. The output inductor is designated L and the
inductor's equivalent series resistance is designated ESR

In the ideal case, the values of Rcsx and Ccsx are chosen
such that (L/ESR

) = (Rcsx)(Ccsx). If this criterion is met,

the current sense signal will have the same shape as the
inductor current, and the circuit can be analyzed as if a sense
resistor with value equal to ESR

was placed in series with

the inductor. However, these components also determine the
ramp signal that is used to prevent pulse skipping and duty
cycle jitter. Choosing (Rcsx)(Ccsx) < (L/ESR

) will result

in the AC portion of the current sense signal being scaled
more than the DC portion. This results in a larger ramp
signal, but the current signal will overshoot during
transients. This will affect transient response, adaptive
voltage positioning and current limit. The COMP pin
voltage will overshoot along with the current signal in order
to maintain the output voltage. The COMP voltage will

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eventually find the correct level for regulation, but the error
will decay with the time constant (Rcsx)(Ccsx). The V

DRP

voltage will also overshoot and response will be slowed,
since the current signal is a component of that voltage. The
single phase current limit will trip earlier since the current
signal appears larger than it should be, and the module
current limit will have a lower threshold for fast transients
than it will for slow transients. Additional external
components in the droop circuit and in the error amp
compensation will correct this condition. Details are provided
in the data sheet section on choosing external components.

Adaptive Voltage Positioning

Adaptive voltage positioning is a technique used to reduce

peaktopeak output deviations during output current
transients. The output voltage is set higher than nominal at
light loads to reduce output voltage sag when load current is
suddenly increased. Similarly, output voltage is set lower
than nominal at heavy loads to reduce overshoot when load
current suddenly decreases. The CS5305 implements
adaptive voltage positioning by placing a resistor divider
between V

DRP

and V

OUT

. The center tap of the divider

connects to V

. These resistors, along with two or three

other external components, implement a lossless droop
voltage function.

Past implementations of adaptive voltage positioning

used a droop resistor. This resistor was placed in series
between the regulation point of the output voltage and the
load. Increasing the current to the load caused the voltage at
the load to droop below the regulation point. The amount of
droop was equal to the change in current multiplied by the
droop resistor value. This method was acceptable for low
values of output current, where the droop resistor provided
a minimal change in voltage without dissipating a great deal
of power. Higher output current levels and tighter droop
voltage requirements in today's microprocessors have
rendered this droop resistor technique unusable. The
lossless technique solves these problems.

The AVP function addresses DC and slow transient output

voltage positioning. Response during the first few hundreds
of nanoseconds of a transient are addressed primarily by the
power stage output impedance, and the ESR and ESL of the
output filter. The ramp size and the error amplifier
compensation control the transition between these two
regions. If ramp size is too large or the error amp is too slow,
there will be a long transition to the final voltage after a
transient. This will be most apparent if the output
capacitance is low.

Figure 28 shows how adaptive positioning works. The

waveform labeled "normal" shows output voltage for a
converter without adaptive voltage positioning. The voltage
sags when current steps up, returns to its nominal value and
then overshoots when the current load is decreased. Using
a slow adaptive positioning circuit can actually worsen
performance. The slow adaptive positioning waveform
above shows the output voltage sag, but the voltage recovers
to its initial value before the adaptive positioning circuit

becomes active. When the load decreases, the overshoot
causes the output voltage to exceed the upper limit. The fast
adaptive positioning waveform shows how AVP can reduce
transient voltage requirements by about one half compared
to a "normal" converter.

Adaptive Positioning

Normal

Fast

Slow

Limits

Figure 28. Adaptive Positioning

Current Limit

The CS5305 features two separate current limit circuits.

First, the perphase current limit terminates topside switch
conduction in a phase if the voltage between any CSx pin
and CS

REF

exceeds a typical value of 90 mV. This provides

fast peak current protection for individual phases. In
addition, the output current signals for all three phases are
summed and filtered to provide an average module current
signal. This signal is compared to a voltage that is
userprogrammable. If this voltage is exceeded, the fault
latch is set and the COMP capacitor is discharged by a 5

current sink until the COMP voltage falls below 0.2 V. The
softstart cycle begins when this threshold is reached, and the
converter will operate in hiccupmode until the overcurrent
condition is cleared.

Error Amplifier

The CS5305 uses the Enhanced V

control method to

offer the fastest and most accurate regulation available. One
of the features of this control method is ease of error
amplifier compensation. A single capacitor placed from the
COMP pin to ground is sufficient to adequately stabilize the
error amplifier.

200

160

120

100

(VY2) in db(V

olts)

Phase(VY2) in Deg

100

1.0 k

10 k

100 k

Frequency in Hz

Figure 29. Error Amplifier Frequency

Response with No Compensation

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170

150

130

110

Phase(VY1)

in Deg

+Result of V

(VY1)

100

1.0 k

10 k

Frequency in Hz

Figure 30. Error Amplifier Frequency

Response with 0.1

F Capacitor

Soft Start/Hiccup Mode

At initial powerup, the COMP voltage is zero. The total

COMP capacitance will begin to charge with a typical
current of 30

A. (There may be more than one capacitor

connected between COMP and ground depending on the
adaptive voltage positioning compensation.) All GATE
outputs are held low until the COMP voltage reaches 0.6 V.
Once this threshold is reached, the GATE outputs are
released to operate normally. In hiccupmode, this will
result in GATE pulses being generated until the module
overcurrent condition reoccurs, and the discharge/Soft Start
cycle begins anew.

Undervoltage Lockout

The CS5305 includes an undervoltage lockout circuit.

This circuit disables the output drivers until V

applied to

the IC reaches a typical value of 9 V. The GATE outputs are
disabled when V

drops below 8 V typical.

Enable

The CS5305 has a dedicated enable pin, in accordance with

the latest VRM specifications. This pin is internally pulled up
to a 3.3 V rail through a blocking diode and a 50 k

resistor.

The blocking diode allows external pull up to a bias voltage
greater than 3.3 V but below 13 V.

Fault Protection Logic

The CS5305 is equipped with sophisticated

faultdetection and protection circuitry to ensure proper
operation in a paralleled VRM environment. In such an
environment, any one of several distinct failures could not
only destroy the VRM that sees the fault, but also those
VRMs that are connected in parallel with the faulted VRM.

Table 1 describes the fault logic circuitry, shown below in

Figure 31.

VID FAULT

ENABLE

UVLO

COMP
DISCHG'D?

OVC

LOCAL
FAULT
LATCH

SHARE
FAULT
LATCH

SHARE
BUS
HIGH?

FAULT

Figure 31. Fault Logic Circuitry

Table 1. Description of Fault Logic

Fault Modes

Stop

Switching

DRVON

Level

PWRGD

Level

SHARE

Controller

Off

COMP Pin

Characteristics

Reset Method

Under Voltage Lockout

yes

low

low via Power Good

window comparator

n/a

5.0

Comp < 0.2 V

VID = 11111

yes

low

low via Power Good

window comparator

n/a

5.0

Comp < 0.2 V

Enable Low

yes

low

n/a

5.0

Comp < 0.2 V

Module Over Current
(set by OCSET)

yes

low

low via Power Good

window comparator

> 3.8 V

5.0

Comp < 0.2 V

Phase Over Current
(0.33 V limit)

terminate

pulse

high

n/a

not affected

External Share Fault
(SHARE > 3.8 V)

yes

low

low via Power Good

window comparator

n/a

2.5 mA

remove external

3.8 V from SHARE

PWRGDS out of win-
dow range

high

low

n/a

not affected

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Gate Outputs

The CS5305 is designed to operate with external gate

drivers. Accordingly, the gate outputs are capable of driving
a 100 pF load with typical rise and fall time of 15 ns.

DRVON

When the CS5305 is used with DRVONcompatible gate

drivers, the ability of the system to survive a fault in a
paralleled environment is greatly increased. The DRVON
signal tells the gate drivers to shut off both FETs while
entering a fault condition. This action takes the faulted VRM
"out of the picture," allowing the system to operate until the
bad module can be replaced.

Digital to Analog Converter (DAC)

The output voltage of the CS5305 module is set by means

of a 5bit, 1% DAC. The DAC pins are internally pulled up
to a 3.3 V rail through a blocking diode and a set of 50 k

resistors. The blocking diode allows external pull up to a
bias voltage greater than 3.3 V and less than 13 V.

The output of the DAC is described in the Electrical

Characteristics section of the datasheet. These outputs are
consistent with the latest VRM specifications. The DAC
produces an output voltage 125 mV lower than the VID code
would indicate in order to produce an accurate PWRGD
output. The relationship between the VID code and the DAC
code is described by Figure 32 shown below. The shaded
area shows the acceptable range of output voltages.

In order to produce a workable VRM using the CS5305,

the designer is expected to use AVP as described earlier to
position the output voltage above the DAC output, resulting
in an output voltage somewhere in the middle of the
acceptable range.

ÉÉÉÉÉÉÉÉ

125 mV

VID code

DAC output

MAX V

OUT

MIN V

OUT

Figure 32. VRM 9.0 Output

Voltage Accuracy Requirements

The latest VRM specifications require a module to turn its

output off in the event of a 11111 VID code. When the DAC

sees such a code, the GATE pins stop switching and go low.
The DRVON signal also goes low, which turns off all FETs
on the module if the FET driver has an enable input. This
condition is described in Table 1.

PWRGD

According to the latest VRM specifications, the PWRGD

signal is to be asserted when the output voltage is within a
window defined by the VID code, as shown in Figure 33.

PWRGD

ÉÉÉ

ÇÇÇ

ÉÉÉÉ

ÇÇÇÇ

0.975

(VID 125 mV)

1.975 V

OUT

HIGH

LOW

PWRGD

2.6% +2.6%

5.0% +5.0%

Figure 33. PWRGD Assertion Window

low

PWRGD

low

PWRGD

high

In addition, certain fault modes must cause PWRGD to go

low to signal the system board that a VRM fault has
occurred. In that sense, the PWRGD signal operates as a
"VRM BAD" signal. These fault modes, as shown in Table 1
above, are ENABL low and CSx out of window.

When the ENABL pin is pulled low, PWRGD is pulled

low to indicate that the VRM is off. DRVON is pulled low
to turn both FETs off if the FET driver has an enable input.

The logic circuitry inside the chip sets PWRGD low only

after a delay period has been passed. A "power bad" event
does not cause PWRGD to go low unless it is sustained
through the delay time, typically 200

s. If the anomaly

disappears before the end of the delay, the PWRGD output
will never be set low.

In order to use the PWRGD pin as specified, the user is

advised to connect external resistors as necessary to limit the
current into this pin to 4 mA or less.

Share Bus

VRM 9.x specifications require that a singlewire share

bus be provided from each module. This bus allows output
current information to be communicated between modules
such that the total load current is shared equally by each
module. The CS5305 employs a proprietary share algorithm
called direct duty cycle control. A block diagram is provided
in Figure 34.

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PWM

LATCH

RESET

SET

GATEx

GATE

DRIVER

PWM

COMPARATOR

BUS AMP

30 mV

ADJUST AMP

CURRENT

SENSE AMP

FROM

OSCILLATOR

COMP

SCOMP

OUT

3.7

CURRENT

SENSE INPUT

3.3 V

OUT

+ V

OFFSET

+ 1

CURRENT SENSE INPUT

Figure 34.

Direct duty cycle control utilizes a masterslave approach

to current sharing. At any given current load, one module
will have a higher share bus voltage than the other modules.
This module acts as the master. It conveys output current
information to the other modules via the share bus. This
information is buffered and provided to the PWM
comparators, thus directly controlling duty cycle for the
slave modules.

The share current sense amplifier allows the user to

customize the share bus transconductance. Current sense
information is provided to the noninverting input from the
3.7

current sense amplifier from each phase. This provides

a representation of the total module current. An external
resistor divider between I

OUT

and ground, centertapped at

programs the share bus voltage for a particular current

level.

The share bus amplifier serves as a buffer and places the

OUT

voltage on the SHARE pin. Note there is a diode in the

schematic between the share bus amplifier and the SHARE
pin. This is an "ideal" diode, and indicates that the share bus
amplifier does not have current sink capability. This allows
the share bus to be driven by the module with the highest
share bus voltage. A 30 mV offset voltage provides noise
immunity to ensure that any given module does not cycle
between master and slave in a random fashion. It also
guarantees that the master module is not driving duty cycle
from the share bus. For the master module, the I

OUT

and

SHARE voltages will be equal. In this case, the 30 mV offset
holds the share adjust amplifier inactive, and the PWM
channel is controlled in the normal manner. The offset
voltage results in a current error between the master and
slave modules, but this error is small compared to the current
share tolerance found in the VRM 9.x specifications.

The share adjust amplifier takes the share bus voltage and

directly drives the PWM comparators of all slave modules
as previously described. The SCOMP pin provides a
connection point for a compensation capacitor for the share
adjust amplifier.

CHOOSING EXTERNAL COMPONENTS

FOR THE CS5305

OCSET

and R

OSC

The R

OSC

lead of the CS5305 provides a fixed 1 V

reference to the user. A resistive divider is connected from
R

OSC

to ground as shown in Figure 35. The center tap of the

divider is connected to the OCSET lead. The total
resistance from the R

OSC

lead to ground programs the

oscillator frequency for the converter according to the chart
in Figure 36.

The resistive divider also sets a voltage on the OCSET lead.

This voltage programs the module overcurrent trip point. The
module overcurrent comparator, or OC Comparator, uses the
OCSET lead voltage as the reference against which the
module output current signal is compared. The output current
of each phase is given as (V

CSx

CSREF

) divided by the

equivalent series resistance of the inductor. The voltage
information (V

CSx

CSREF

) is gained up by a factor of 3.7

and summed for all three phases at the noninverting input of
the OC Comparator. The fault latch is set if the module
overcurrent limit is exceeded. This results in "hiccupmode"
operation until the overcurrent condition is cleared.

OCSET

OSC

OCSET

OSC

= R1 + R

OCSET

Figure 35.

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Figure 36. F

OSC

vs. R1 + R

OCSET

(kHz)

100

R1 + R

OSCSET

)

300

400

500

600

700

800

900

200

Additionally, the total value of resistance between R

OSC

and ground also programs the V

pin bias current. V

bias

current is equal to 0.333 V divided by the total resistance
from R

OSC

to ground. This current is used to generate the

droop function in the adaptive voltage positioning circuitry
and is discussed further in that section.

Current Sense Components

Current sense components are chosen for two reasons.

First, the value of R

CSx

and C

CSx

should be chosen to meet

the criterion:

(RCSx)(CCSx)

(L) (ESRL)

where L is the inductor value and ESR

is the inductor

equivalent series resistance. Meeting this criterion will
ensure that the module overcurrent limit is not exceeded
during current transients. Second, R

CSx

and C

CSx

should be

chosen to add a small amount of ramp to the system. This
will provide stable, jitterfree operation. The amount of
ramp voltage required depends on several factors: supply
voltage, output voltage (DAC code), switching frequency
and board layout all affect the amount of artificial ramp
required to some degree. The power supply designer should
be aware that choosing the value of artificial ramp is a
tradeoff. As artificial ramp amplitude increases, the system
becomes less prone to duty cycle jitter, but transient
response will suffer. Adding 20 mV of artificial ramp is a
good compromise and can be used to start design.

The current sense ramp is generated from the square wave

obtained at the switching node of each phase by using an RC
filter. The RC filter components for the CSx leads should be
chosen to satisfy the following formula:

RCSx CCSx

(VOUT) 1

VOUT VCC

(fOSC)(VRAMP)

Choose a convenient standard value for C

CSx

and solve for

the value of R

CSx

. Each of the three output phases requires

its own RC combination.

An RC filter is also required for the CS

REF

connection.

This filter may use the same value of capacitance identified

for the CS1, CS2 and CS3 leads, but the value of resistance
should be one third that of R

CSx

RCSREF

RCSx 3

This change is necessary to compensate for the difference

in bias current between the CS

REF

lead and each CSx lead.

The schematic in Figure 37 shows the connection of these
components.

CSx

CSREF

= R

CSx

REF

OUT

Switch

Node x

CSx

Figure 37.

Share Bus Components

Five external components are required to implement the

moduletomodule current share function. These
components

set the current sense load line, provide the share

bus pulldown and compensate the share adjust amplifier.

The share current sense amplifier monitors the total

module current and provides a DC voltage output
proportional to that current. The share sense amplifier gain
is programmable and allows the user to set the share bus
transconductance. It is important that all modules in a
system have a share current load line that approximates that
of all the other modules to ensure accurate
moduletomodule

current sharing. Let us arbitrarily set the

share bus maximum voltage for full load at 2 V. If a module
is designed to provide 81 A at full load, the module share
transconductance should be 81 A/2 V or 40.5 A/V. Two
resistors and a capacitor set the share current sense amplifier
gain. The resistors set the DC gain while the capacitor
provides a zero to minimize errors due to noise.

The total module current is measured as described in the

section dealing with the OCSET current limit function. That
is, each phase within a module generates a voltage between
the CSx and CS

REF

leads that is proportional to the current

flow in the output inductor and the inductor's ESR:

VCSx

VCSREF

(IL)(ESRL)

This signal is amplified by a factor of 3.7 for each phase

and then summed for all three phases. This signal is provided
as input to the share current sense amplifier. If we assume
that all three phases are sharing current equally within a
single module, the input to the share current sense amplifier
can be expressed as:

VIN(SENSE)

11.1(VCSx

VCSREF)

11.1(IL)(ESRL)

3.7(IOUT)(ESRL)

If we set I

equal to the maximum per phase current at full

load, and if we know the value of ESR for our inductors, we

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can calculate the required share current sense amplifier
gain as:

AV(SHARESENSE)

share maximimum voltage

VIN(SENSE)

As an example, let us again consider the case for a module

providing full load current of 81 A. Each output phase is
conducting 27 A. If we assume ESR = 1.5 m

then input to

the share current sense amplifier is (11.1)(27 A)(1.5 m

) =

0.45 V. The required share current sense amplifier gain is
then 2 V/0.45 V = 4.44.

IOUT

IFB

IN(SENSE)

OUT

Figure 38.

From the schematic in Figure 38, we derive the DC gain as:

AV(SHARESENSE)

4.44

RIOUT RIFB

)

This specifies that R

IOUT

should be 3.44 times greater than

IFB

Another important consideration is the type of resistor

selected for R

IFB

. The thermal performance of R

IFB

must

match that of whatever sense element is being used to monitor
module current. Inductive sensing has been shown to be
reasonably accurate, but copper's thermal coefficient of
resistivity is approximately +4000 parts per million per

(0.4% per

C). In order to maintain accurate control of the

share bus over temperature, R

IFB

must have a similar thermal

coefficient. This requires a positive temperature coefficient
element such as the KOASpeer LT73. If a standard sense
resistor is used in series between the inductor and the load,
there is no need to use special resistors for sensing, but
efficiency will suffer due to power dissipation in the sense
resistor.

As regards the value of C

IOUT

, it should be noted that the

complete transfer function for the share current sense
amplifier in Figure 38 is:

AV(SHARESENSE)

RIOUT

RIFB(1

)

sCIOUT RIOUT)

)

IOUT

causes the gain for high frequency noise to

decrease, thus quieting the share bus.

The share resistor provides a passive pulldown on the

SHARE lead. This allows the share bus voltage to be pulled
all the way down to ground. The share resistor is selected to
satisfy a number of criteria. First, the resistor cannot be made
too small. The SHARE lead source current is guaranteed to
be above 1 mA and must be capable of driving the SHARE

lead voltage to 3 V. The share bus of one module serves as
master to all and drives the total resistance of all SHARE
leads. Thus, the total impedance of all share resistors should
be made greater than or equal to 3 k

. That is,

3 k

W w

RSHARE N

where N is the maximum number of modules that can be
placed in parallel as defined by the designer. As an
example, if ten is the maximum number of modules that
may be paralleled, then the minimum value of R

should be 30 k

The share resistor should also not be made too large, since

this is the only pulldown on the SHARE lead. Transient
response of the share bus is limited by the RC time constant
of the share resistance and any parasitic capacitance found
on the SHARE line between modules.

Droop Components

The CS5305 offers adaptive voltage positioning. This

feature allows the output voltage to be set at different levels
according to the amount of current being provided by the
module. The output voltage is somewhat higher than
nominal under no load or light load conditions and
somewhat lower than nominal under heavy load conditions.
Both set points must fall within the Power Good window.
The adaptive positioning allows for overshoot and
undershoot conditions that occur during load current
transients and results in a reduction in the peaktopeak
V

OUT

voltage excursion during load current transients.

Three components are required to implement DC

adaptive voltage positioning. Resistor R

is connected

between the module V

OUT(SENSE)+

lead and the V

lead.

Resistor R

DRP

is connected between the V

DRP

lead and

lead. Resistor R

VSENSE

is connected between the

OUT(SENSE)+

lead and the module V

OUT

lead. These

connections are shown in Figure 39.

Figure 39.

DRP

VSENSE

OUT

OUT(SENSE)+

DRP

The first step in choosing these components is to select the

appropriate noload and fullload output voltage set points
for the particular DAC code being used. Additionally, the
values of R

OSC

and R

OCSET

should be known, as should

ESR of the output inductors and the fullload output current.

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Figure 40.

DRP

V(DAC)

OUT

OUTPUT

STAGE

DRP

I(V

)

As was previously noted, the total value of resistance

between the R

OSC

pin and ground sets the V

lead bias

current according to:

I(VFB)

0.333 V (ROSC

)

ROCSET)

Referring to Figure 40, the V

DRP

lead voltage is equal to

the DAC voltage plus the current sense information. Under
no load conditions, the V

DRP

and V

pin voltages are equal,

and the entire V

bias current flows between

OUT(SENSE)+

and V

through R

. Because the V

bias

current sinks into V

, the output voltage is forced to be

higher than the DAC voltage, and so the value of R

can be

calculated as:

RFB

(VOUT no load set point

VDAC) I(VFB)

With R

chosen, we can now select the value of R

DRP

If we again refer to Figure 40, we can use Kirchoff's
Current Law at the V

node to find that the value of R

DRP

is defined as:

RDRP

(full load current)(3.7)(ESRL)(RFB)

(RFB)(I(VFB))

)

V(DAC)

VOUT full load set point

VSENSE

is used to ensure that a connection between

OUT

and V

OUT(SENSE)

always exists. This ensures that the

module will operate correctly in the event that the
V

OUT(SENSE)

connection is broken. The moduletoload

interface and the number of modules placed in parallel
determine the value of R

VSENSE

. The CS5305 is specified to

operate correctly with up to 55 mV dropped across the
module connector. It is assumed that the maximum current
allowed to flow in this connection to the load is 1 mA.

RVSENSE

55 mV (1 mA N)

where:

N = the number of modules to be paralleled.

If four modules are to be paralleled, each contributes a

maximum of 250

A to this connection, and so R

VSENSE

55 mV/250

A = 220

. This component is placed to ensure

the VRM module will regulate correctly if the module
V

OUT(SENSE)+

connection to the load is opened.

The transient droop performance should be checked next.

Performance should be verified using the transient test tool
typically provided in a microprocessor development kit.
True transient performance can be masked even at test
frequencies as low as 2 kHz. It should be possible to modify

the test tool so a function generator can drive it. Using lower
frequency (approximately 100 Hz) and lower duty cycle
(10%) allow the designer to better observe the true settling
behavior of the VRM module.

It may be necessary to add some filtering components to

the droop voltage divider. These components cause the AC
and DC gain from the current sense circuitry to match and
allow the user to tailor the droop output voltage
performance.

There

are two methods for tuning droop performance. The

first is illustrated in Figure 41. In this case, capacitors C

DRP

and C

are placed in parallel with R

DRP

and R

. A third

capacitor C

DRCMP

is connected between the COMP and

DRP

leads. The first two capacitors correct any gain errors

introduced in the selection of current sense components
Rcsx and Ccsx. Values for these components are defined as:

CFB

L ((RFB)(ESRL))

and

CDRP

((CCSx)(RCSx)) RDRP

The capacitor between V

DRP

and COMP allows the user

to finetune the transition between "fast" AVP and the
slower positioning set by resistors R

DRP

and R

. This

capacitor may or may not be required and is empirically
chosen based on the finetuning procedure described below.
A value of 1 nF is recommended as an initial value.

Figure 41.

DRP

VSENSE

OUT

OUT(SENSE)+

DRP

DRCMP

COMP

Set up the circuit to be tested with a DVM and

oscilloscope to the output. Have the scope set to DC input
and set its offset so a resolution of at least 100 mV/div is used
and the output is visible on the screen.

Using a DVM, measure the output voltage with no load.

If this value differs from the expected value, adjust R

until

the nominal value is reached. Once this is set, mark this DC
level on the scope with a cursor.

Next, measure the output voltage with full DC load. If this

value deviates from the expected value, adjust R

DRP

until

the nominal value is reached. Once this is set, mark this DC
level on the scope with another cursor.

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Figure 42.

No Load Cursor Marker

Full Load Cursor Marker

Trace 1: Optimal
Trace 2: C

too large

Trace 3: C

too small

Trace 4: C

DRCMP

too large, C

COMP

too small

Trace 5: C

DRCMP

too small, C

COMP

too large

Using the transient test tool, set up a current load step from

low current (1 A) to maximum load at the slew rate being
designed for. Set the current step at about 100 Hz with a duty
cycle of 10%. Converter response should be similar to that
shown in Figure 42.

Next, determine if there is a "bump" (trace 4 or trace 5) in

the output. Adjust C

COMP

and C

DRCMP

to flatten out this

bump. If the "bump" is negative (trace 5), make C

DRCMP

slightly larger and C

COMP

slightly smaller. If you see a

positive "bump" (trace 4), make C

DRCMP

slightly smaller

and C

COMP

slightly larger. If performance is better without

DRCMP

, just make C1 larger.

Once the bump is removed, look to see if the "pulse step"

magnitude is larger or smaller than the DC level (trace 2 or
trace 3). Make C

slightly larger if the AC gain (trace 3) is

too large or slightly smaller if the AC gain (trace 2) is too
small. Once the output response resembles the "optimal"
trace (trace 1), the controller has been optimized for the
design from a static and dynamic response.

If the output appears to be jittering slightly prior to

optimizing transient response, make the previous
adjustments first, since they may solve the problem. If the
problem persists, decreasing the value of Rcsx across the
inductor will increase ramp amplitude, and jitter
performance should improve with increased ramp.

The second method uses a capacitor to "square up" the

COMP waveform and a series resistor and capacitor to tune
the V

DRP

waveform. These components are chosen

empirically based on observations of COMP and V

DRP

performance.

First, set the test tool for a load current transient from no

load (1 A) to full load and observe the COMP waveform.

The COMP waveform should ideally be flat, or at worst
decrease slightly during a current increase transient. The
principle at work here is that the increase in current sense
information will generate a voltage that should exactly
cancel the droop voltage, and thus the COMP capacitor
voltage should not change. In reality, it is unlikely that every
manufactured module can be built to perfectly compensate
the droop voltage, and so the COMP voltage should exhibit
a small amplitude square wave during transient conditions.
If the COMP voltage is decreasing gradually, the current
sense information is too small to fully compensate for the
droop voltage, and the designer should add a capacitor
between V

OUT

and COMP. This capacitor is chosen

empirically, with 1 nF a good starting point. This capacitor
will pull the COMP pin down initially and "square up" the
COMP waveform as shown in Figure 43.

Figure 43.

Current Transient

COMP Ideal Waveform

COMP Uncorrected

Waveform

OUT

Uncorrected

Waveform

COMP Corrected

Waveform

OUT

Corrected

Waveform

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In a similar manner, if the current information is too large,

the COMP voltage will rise to compensate. Again, a square
wave is preferable to a slow change in the COMP voltage,
and placing a capacitor between V

DRP

and COMP will

"square up" the COMP waveform as shown in Figure 44.

Figure 44.

Current Transient

COMP Ideal Waveform

COMP Uncorrected

Waveform

OUT

Uncorrected

Waveform

COMP Corrected

Waveform

OUT

Corrected

Waveform

Once the COMP waveform has been squared up, it is

necessary to check the V

DRP

waveform. The V

DRP

waveform is dependent on the choice of ramp
components. If these components have been chosen such
that (R

CSx

)(C

CSx

) = L / ESR

, the V

DRP

waveform should

be a square wave that matches the current step. At this
point, the V

OUT

waveform should also be a square wave

and transient performance should be optimized.

If (R

CSx

)(C

CSx

) < L / ESR

, the V

DRP

waveform will be

faster than current step. The V

DRP

voltage will exhibit a fast

rise followed by an exponential droop down to a DC level,
as shown in Figure 45. This waveform has the effect of
telling the system that transient current signals are larger
than the true current. Response will be slowed, and V

OUT

will overshoot until the error amplifier "catches up". In this
case, it is desirable to push the V

pin down, so that COMP

voltage is forced up and duty cycle is reduced slightly. This
is done by placing a series RC filter across resistor R

Figure 45.

Current Step

DRP

CSx

)(C

CSx

) < L/ESR

If (R

CSx

)(C

CSx

) > L / ESR

, the V

DRP

waveform will be

slower than the current step. V

DRP

will exhibit an initial

spike, but the voltage will then exponentially rise toward its
correct DC level, as shown in Figure 46. This waveform
effectively tells the system that the current signal is smaller
than the true current, and response will be faster than
optimal. V

OUT

will then undershoot. In this case, forcing

up so COMP voltage decreases results in increasing

output duty cycle. The series RC filter is now located in
parallel with R

DRP

Figure 46.

Current Step

DRP

CSx

)(C

CSx

) > L/ESR

These components are chosen empirically. The fastest

way to optimize the design is to start with a 1 nF capacitor
and a 500 k

potentiometer and "dial in" performance.

Error Amplifier Compensation

Error amplifier compensation is very simple using the

enhanced V

control architecture. A single 0.1

F capacitor

from the COMP lead to ground is usually sufficient. As an
alternative, a resistor and capacitor in series between COMP
and ground may improve output voltage positioning during
current transients. The resistance will speed up the effective
slew rate of the error amplifier output.

The COMP capacitor also provides soft start and

hiccupmode timing. At startup, the COMP capacitance
must charge from ground through a typical channel startup
offset of 0.6 V before the GATE outputs are allowed to begin
switching. The COMP capacitance includes both the COMP
capacitor and any droop compensation capacitance that may
be connected to the COMP pin. The typical soft start time
can then be approximated as:

TSOFTSTART(ms)

20 CCOMP(TOTAL)(

Hiccup timing has a similar equation. During

hiccupmode, the COMP voltage traverses between the
fault reset threshold (approximately 0.2 V) and the channel
startup offset voltage. When the fault circuitry becomes
active, the COMP capacitor is discharged with a 5

current until the fault reset threshold is reached. The time
this initial discharge takes is variable depending on the
COMP voltage when the fault occurred. Once the reset
threshold is reached, the COMP capacitor is charged with
the 30

A current until the startup offset voltage is reached.

The GATE outputs will begin to pulse, quickly ramping the
inductor current. The fault circuitry can then redetect the
fault condition some number of GATE pulses later if it is still
present. Thus, the period of the fault hiccup mode is
approximately defined as:

THICCUP(ms)

93.3 CCOMP(TOTAL)(

Period is only approximately defined since the number of

GATE pulses between restart and redetection of a fault
condition is unpredictable.

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Inductors

There are many factors to consider when choosing the

output inductors. Maximum load current, core and winding
losses, ripple current, short circuit current, saturation
characteristics, component height and cost are all variables
that the designer should consider. However, the most
important consideration in designing for the VRM 9.x
specifications may be the effect inductor value has on
transient response.

The amount of overshoot or undershoot exhibited during

a current transient is defined as the product of the current
step and the output filter capacitor ESR. To some degree,
adaptive voltage positioning is used to "preposition" the
output voltage so the voltage step during a current transient
will not cause the output voltage to exceed the Power Good
window. However, adaptive positioning will not completely
eliminate the overshoot or undershoot conditions, and
choosing the inductor value appropriately can minimize the
amount of energy that must be transferred from the inductor
to the capacitor or viceversa. In the subsequent paragraphs,
we will determine the minimum value of inductance
required for our system and consider the tradeoff of ripple
current vs. transient response.

In order to choose the minimum value of inductance, input

voltage, output voltage and output current must be known.
Most computer applications use reasonably well regulated
bulk power supplies so that, while the equations below
specify V

IN(MAX)

or V

IN(MIN)

, it is possible to use the

nominal value of V

in these calculations with little error.

Current in the inductor while operating in the continuous

current mode is defined as the load current plus ripple
current.

ILOAD

)

IRIPPLE

The ripple current waveform is triangular, and the current

is a function of voltage across the inductor, switch FET
ontime and the inductor value. FET ontime can be defined
as the product of duty cycle and switch frequency, and duty
cycle can be defined as a ratio of V

OUT

to V

. Thus,

IRIPPLE

(VIN

VOUT)VOUT

(fOSC)(L)(VIN)

Peak inductor current is defined as the load current plus

half of the peak current. Peak current must be less than the
maximum rated FET switch current, and must also be less
than the inductor saturation current. Thus, the maximum
output current for a single phase can be defined as:

IOUT(MAX)

ISWITCH(MAX)

VIN(MAX)

VOUT VOUT

2 fOSC L VIN(MAX)

Since the maximum output current must be less than the

maximum switch current, the minimum inductance required
for a single phase can be determined.

L(MIN)

(VIN(MIN)

VOUT)VOUT

(fOSC)(ISWITCH(MAX))(VIN(MIN))

This equation identifies the value of inductor that will

provide the full rated switch current as inductor ripple
current, and will usually result in inefficient system
operation. The system will sink current away from the load
during some portion of the duty cycle unless load current is
greater than half of the rated switch current. Some value
larger than the minimum inductance must be used to ensure
the converter does not sink current. Choosing larger values
of inductor will reduce the ripple current, and inductor value
can be designed to accommodate a particular value of ripple
current by replacing I

SWITCH(MAX)

with a desired value of

RIPPLE

L(RIPPLE)

(VIN(MIN)

VOUT)VOUT

(fOSC)(IRIPPLE)(VIN(MIN))

However, reducing the ripple current will cause transient

response times to increase. The response times for both
increasing and decreasing current steps are shown below.

TRESPONSE(INCREASING)

(L)(

IOUT)

(VIN

VOUT)

TRESPONSE(DECREASING)

(L)(

IOUT)

(VOUT)

Inductor value selection also depends on how much output

ripple voltage the system can tolerate. Output ripple voltage
is defined as the product of the output ripple current and the
output filter capacitor ESR. However, since the CS5305 has
three paralleled phases, the net effect is that the switching
frequency as seen by the output capacitance is tripled relative
to the CS5305 operating frequency. This is because each
phase switches in sequence and the ripple currents in each
phase are superimposed on the output capacitance. This is
illustrated graphically in Figures 45 and 46.

Thus, output ripple voltage can be calculated as:

VRIPPLE

ESRC IRIPPLE

ESRC VIN

VOUT VOUT

3 fOSC L VIN

It is also important to note that the maximum value of

inductor ESR is limited by the singlephase pulsebypulse
current limit. The specified minimum value for this
parameter is 80 mV, so the maximum inductor ESR is:

ESRL(MAX)(in ohms)

(0.08 V)

single phase current limit value in Amps

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Figure 47.

PHASE 1 SWITCH NODE

PHASE 2 SWITCH NODE

PHASE 3 SWITCH NODE

SUPERIMPOSED PHASE

INDUCTOR CURRENTS

PHASE 1 CURRENT
PHASE 2 CURRENT
PHASE 3 CURRENT

OUTPUT RIPPLE CURRENT

Finally, we should consider power dissipation in the

output inductors. Power dissipation is proportional to the
square of inductor current:

2
PHASE

)(ESRL)

The temperature rise of the inductor relative to the air

surrounding it is defined as the product of power dissipation
and thermal resistance to ambient:

T(inductor)

(Ra)(PD)

Ra for an inductor designed to conduct 20 A to 30 A is

approximately 45

C/W. The inductor temperature is given as:

T(inductor)

+ D

T(inductor)

)

Tambient

Output Filter Capacitors

Each microprocessor manufacturer specifies output filter

capacitors for the motherboards. In addition, the designer
may need to add some output capacitance on the VRM
module. These added output capacitors would serve to
reduce the noise floor and help ensure jitterfree operation.
If needed, one or two ceramic capacitors should be
sufficient. They should have a 4 WVDC rating. Large
amounts of bulk capacitance placed on the VRM module are
not useful, since the impedance of the VRM connector exists
between the module and the load. Low equivalent series
resistance is important since output ripple voltage and
response to output current transients are largely dependent
on this parasitic parameter.

Bypass Filtering

A small RC filter should be added between module V

and

the V

input to the CS5305. A 10

resistor and a 0.1

capacitor should be sufficient to ensure the controller IC does
not operate erratically due to injected noise.

Module Input Filter Capacitors

The input filter capacitors for the VRM module provide

a charge reservoir that minimizes supply voltage variations
due to changes in current flowing through the switch FETs.
These capacitors must be chosen primarily for ripple current
rating.

Figure 48.

OUT

IN(AVE)

RMS(CIN)

CONTROL

INPUT

OUT

Consider the schematic shown in Figure 48. The average

current flowing in the input inductor L

for any given

output current is:

IIN(AVE)

(IOUT)(VOUT VIN)

(IOUT per phase)(n)(D)

where:

D = duty cycle,

n = number of phases.

Input capacitor current is positive into the capacitor when

the switch FETs are off, and negative out of the capacitor
when the switch FETs are on. When the switches are off,
I

IN(AVE)

flows into the capacitor. When the switches are on,

capacitor current is equal to the perphase output current
minus I

IN(AVE)

. If we ignore the small current variation due

to the output ripple current, we can approximate the input
capacitor current waveform as a square wave. We can then
calculate the RMS input capacitor ripple current:

IRMS(CIN)

2
IN(AVE)

)

IOUT per phase

IIN(AVE) 2

2
IN(AVE)

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The input capacitance must be designed to conduct the

worst case input ripple current. This will require several
capacitors in parallel. In addition to the worst case current,
attention must be paid to the capacitor manufacturer's
derating for operation over temperature.

As an example, let us define the input capacitance for a

12 V to 1.7V conversion at 81 A, or 27 A per phase at an
ambient temperature of 60

C. A droop voltage of 90 mV to

1.61 V and efficiency of 80% is assumed. Average input
current in the input filter inductor is:

IIN(AVE)

(27 A)(3 phases)(1.61 V 12 V)

80%

10.868 A

Input capacitor RMS ripple current is then

IIN(RMS)

10.8682

)

1.61 V

12 V

27 A

10.868 A 2

10.868 A2

13.347 A

If we consider a Sanyo SP series capacitor, the ripple

current rating for a 16SPS100M capacitor is 2820 mA at
100 kHz and 45

C. The derating factor is 0.85 for operation

up to 65

C, resulting in an effective ripple current rating of

2397 mA. We determine the number of input capacitors by
dividing the ripple current by the percapacitor current
rating:

Number of capacitors

13.347 A 2.397 A

5.52

A total of at least 6 capacitors in parallel must be used to

meet the input capacitor ripple current requirements.

Output Switch FETs

Output switch FETs must be chosen carefully, since their

properties vary widely from manufacturer to manufacturer.
The CS5305 system is designed assuming that a FET driver
IC and nchannel FETs will be used. The FET
characteristics of most concern are the gate
charge/gatesource threshold voltage, gate capacitance,
onresistance, current rating and the thermal capability of
the package.

FET driver ICs have a limited drive capability. If the

switch FET has a high gate charge, the amount of time the
FET stays in its ohmic region during the turnon and
turnoff transitions is larger than that of a low gate charge
FET, with the result that the high gate charge FET will
consume more power. Similarly, a low onresistance FET
will dissipate less power than will a higher onresistance
FET at a given current. Thus, low gate charge and low
R

DS(ON)

will result in higher module efficiency and will

reduce heat being generated by the VRM module.

It can be advantageous to use multiple switch FETs to

reduce power consumption. By placing a number of FETs in

parallel, the effective R

DS(ON)

is reduced, thus reducing the

ohmic power loss. However, placing FETs in parallel
increases the gate capacitance so that switching losses
increase. As long as adding another parallel FET reduces the
ohmic power loss more than the switching losses increase,
there is some advantage to doing so. However, at some point
the law of diminishing returns will take hold, and a marginal
increase in efficiency may not be worth the board area
required to add the extra FET. Additionally, as more FETs
are used, the limited drive capability of the FET driver will
have to charge a larger gate capacitance, resulting in
increased gate voltage rise and fall times. This will affect the
amount of time the FET operates in its ohmic region and will
increase power dissipation.

The following equations can be used to calculate power

dissipation in the switch FETs.

For ohmic power losses due to R

DS(ON)

PON(TOP)

(RDS(ON)(TOP))(IRMS(TOP))2(n)

(number of topside FETs per phase)

PON(BOTTOM)

RDS(ON)(BOTTOM) IRMS(BOTTOM) 2 n)

number of bottomside FETs per phase

where:

n = number of phases.

Note that R

DS(ON)

increases with temperature. It is good

practice to use the value of R

DS(ON)

at the FET's maximum

junction temperature in the calculations shown above.

IRMS(TOP)

2
PK

(IPK)(IRIPPLE)

)

2
RIPPLE

IRMS(BOTTOM)

2
PK

(IPKIRIPPLE)

)

2
RIPPLE

IRIPPLE

(VIN

VOUT)(VOUT)

(fOSC)(L)(VIN)

IPEAK

ILOAD

)

IRIPPLE

IOUT

)

IRIPPLE

where:

D = Duty cycle.

For switching power losses:

nCV2(fOSC)

where:

n = number of switch FETs (either top or bottom) per phase,

C = FET gate capacitance,

V = maximum gate drive voltage (usually V

OSC

= switching frequency.

CS5305

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External FET Driver

The CS5305 is designed such that an external FET driver

IC is required. The GATE pin outputs are designed to drive
a 100 pF load, and do not have sufficient drive capability to
directly drive the gates of switch FETs. The GATE outputs
have a typical output high voltage of 2.5 V, so the turnon
threshold of the FET driver should be approximately 2 V.
The GATE outputs are also phased such that the FET driver
IC should turn on the topside nchannel FET when the
GATE output goes high. The bottomside nchannel FET
should be on when the GATE output is below the FET driver
IC turnon threshold.

Additionally, the CS5305 provides a signal called

DRVON that can be connected to the ENABLE pin of FET
drivers that offer an enable feature. If the FET driver's
ENABLE input is high, the FET driver output is determined
by the GATE input, and the switch FETs are driven
according to the conditions described above. If the FET
driver's ENABLE input is low, all switch FETs are turned
off and no current is conducted to the load. This DRVON
signal is a logic output from the CS5305. DRVON goes high
when all internal functions of the CS5305 are operating
correctly and the IC is not in fault mode. A table of the
DRVON logic may be found in the Theory of Operation
section.

Choosing a FET driver IC with an enable feature

significantly improves system reliability, since a faulty
module is essentially disconnected from the load.

SGND Resistor

The moduletoload interface and the number of modules

placed in parallel determine the value of R

SGND

. The

CS5305 is specified to operate correctly with up to 55 mV
dropped across the module connector. It is assumed that the
maximum current allowed to flow in this connection to the
load is 1 mA.

RSGND

55 mV (1 mA N)

where:

N = the number of VRM modules to be paralleled.

If four modules are to be paralleled, each contributes a

maximum of 250

A to this connection, and so,

RSGND

55 mV 250

220

This component is placed to ensure the VRM module will

regulate correctly if the module V

OUT(SENSE)

connection

to the load is opened.

Layout Considerations

Enhanced V

performs best under dynamic load

conditions if current ramp is kept small. However, this may
lead to pulsewidth jitter or pulse skipping, particularly as
the ambient noise level at the control circuit increases. This
is a complicated design tradeoff that can not be
mathematically characterized, and it is crucial to have a
"quiet" layout. Following the design/layout guidelines
below will provide the best system performance. Refer to
Figure 50 for a layout example and to page 2 for the
associated schematic. Numbers in parentheses refer to IC
pin numbers. Component names refer to the reference
designators for the application schematic.

1.Noise across the PWM comparator inputs needs to be

low or pulse width jitter will occur. Referring to the
block diagram, the CS

REF

pin (7) and the COMP pin

(14) present external information to the PWM
comparator. Any differential signal across these pins
is expressed directly across the PWM comparator,
which may cause pulsewidth jitter or pulse skipping.
The solution is to provide a dedicated Kelvin
connection for sensing the VRM's V

OUT

. The IC's

GND pin (28) and COMP capacitance need a
dedicated sense line to V

OUT

, in effect making the IC

and COMP capacitance V

OUT

groundreferenced.

This is desirable since the fast feedback path through
CS

REF

is connected to V

OUT+

and is therefore also

OUT

groundreferenced. Furthermore, a ground

strip under the IC is desirable since the COMP pin is
located at the opposite corner of the IC from the GND
pin. This ground strip further reduces the ambient
noise level of the CS5305 along with providing a
good connection from COMP return to GND and
V

OUT

. Following this guideline will provide the

most system improvement from a layout standpoint.

CS5305

http://onsemi.com

Figure 49.

OUT+

sense

OUT

sense

OUT+

sense

OUT

sense

2.Differential noise across the PWM comparator can be

further reduced if the V

OUT+

and V

OUT

sense lines

going to CS

REF

and GND are paralleled to minimize

loop area. V

OUT+

ripple information provided to the

PWM comparator via the CS

REF

pin needs to be

symmetric for all three phases or poor current sharing
between phases will occur. This can be accomplished
by placing the V

OUT+

and V

OUT

sense locations

symmetrically with respect to the three output
inductors. See Figure 49.

3.Frequency jitter could occur if the R

OSC

pin (2) and

OCSET pin (1) components are not properly located.
Most layouts will have two resistors in series from
R

OSC

to GND. Keep these two components as close

as possible to the IC and ensure a short ground
connection to the IC GND. Provision for a small cap
(1000 pF or less) from R

OSC

to GND can be placed

although this is rarely needed. If the R

OSC

capacitor

value is too large, the R

OSC

voltage reference will

oscillate.

4.The V

(23) bypass capacitor (0.1

F or greater)

should be located as close as possible to the IC. This
capacitor's connection to GND must be as short as
possible. The most effective way to implement this
tight component placement is to via the GATE1, 2, 3
and DRVON runs to internal layers right at the IC
pins.

5.The switch nodes of all three phases must be sensed for

inductive current sensing. Care should be given to
how this information is brought to the CS5305.
Switch node voltages should not be routed
underneath or near the IC; however, the resistors in
the RC filter of CS1, 2, 3 must be reasonably close to
their associated capacitors so noise pickup on the
CS1, 2, 3 pins is minimized. The best solution is to
locate the RC filter capacitors close to the CS1, 2, 3
pins and to place the respective resistors off to the side
of the IC.

6.A positive temperature coefficient thermistor can be

used for R11 (see Share Bus section) to compensate
for thermal variation in the inductor ESR. This

component should be placed near the one of the
inductors to achieve the best thermal coupling, and so
the best current sharing performance. Remote
placement with respect to the IC requires dedicated
parallel runs of GND and I

to reduce share bus

noise sensitivity.

Thermal Considerations

Typically, the controller IC and the FET gate drivers do

not dissipate significant amounts of power, and do not
contribute greatly to module power dissipation. The main
components of concern are the switch FETs and the
inductors.

We have already reviewed the power calculations for

these components, but we haven't related them to a thermal
solution. Standards exist limiting the maximum VRM
printed circuit board temperature (105

C is common), and

thus power dissipation becomes a thermal consideration in
addition to playing a part in overall module efficiency.

Power dissipation on the VRM results in heat radiation

to the surrounding air. Power dissipated by the components
is conducted to the PCB. The PCB acts as a heat sink and
provides a larger surface area for heat exchange to the
surrounding air. The PCB temperature is dependent on total
PCB power dissipation, the surface area of the PCB
available to act as a heat sink, the ambient temperature of
the surrounding air and the thermal resistance to ambient of
the PCB.

While it is possible to model power dissipation on the PCB

for efficiency purposes, it is very difficult to accurately
model thermal performance. In particular, thermal
resistance to ambient of the PCB varies widely. This
parameter depends on many factors: board shape, size and
material; copper weight; amount of exposed copper;
insulating characteristics of the solder mask layers; air flow
properties (amount, direction, PCB orientation to the
airflow); and even whether a particular component is
"hidden" behind others. In reality, modeling PCB resistance
to ambient is highly complex and the best way to guarantee
thermal performance is to actually build prototypes and
measure it directly.

CS5305

http://onsemi.com

Figure 50. Sample Layout

Additional Information

Several additional resources are available to make system

design with the CS5305 a simpler task. The power supply
designer is invited to obtain the following documents and
files from ON Semiconductor.

1.AND8045/D, "Enhanced V

Multiphase SMPS for

Microprocessor." This application note provides
details on the theory of operation, selection of
components, layout practices and thermal
management strategies necessary to design power
supplies with the CS5305 controller.

2."Excel Spreadsheet Method for Choosing CS5305

External Components". This Excel spreadsheet that
can be used to generate a firstpass schematic design
for VRM 9.x designs based on user input, and is
available from the factory.

3."Excel Spreadsheet Method for CS5305 Power Budget

Optimization". This Excel spreadsheet that can be
used to calculate power dissipation in all the
highpower dissipation components (including metal
traces). This allows the design to be optimized for
power/thermal management, and is available from the
factory.

CS5305

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PACKAGE DIMENSIONS

0.025

0.25

SEATING

PLANE

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSIONS.

4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS

OF B DIMENSION AT MAXIMUM MATERIAL

CONDITION.

DIM

MIN

MAX

MILLIMETERS

2.35

2.65

0.13

0.29

0.35

0.49

0.23

0.32

17.80

18.05

7.40

7.60

1.27 BSC

10.05

10.55

0.41

0.90

PIN 1 IDENT

0.10

SO28L

DW SUFFIX

CASE 751F05

ISSUE F

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be
validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
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attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

JAPAN: ON Semiconductor, Japan Customer Focus Center

4321 NishiGotanda, Shinagawaku, Tokyo, Japan 1410031
Phone: 81357402700
Email: r14525@onsemi.com

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local
Sales Representative.

CS5305/D

Patents Pending.
V

is a trademark of Switch Power, Inc.

Literature Fulfillment:

Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 3036752175 or 8003443860 Toll Free USA/Canada
Fax: 3036752176 or 8003443867 Toll Free USA/Canada
Email: ONlit@hibbertco.com

N. American Technical Support: 8002829855 Toll Free USA/Canada

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