2001 OSRAM Opto Semiconductors Inc. San Jose, CA
www.infineon.com/opto 408-456-4000
OSRAM Opto Semiconductors GmbH & Co. OHG Regensburg, Germany
www.osram-os.com +49-941-202-7178
1
July 5, 2001-14
HIGH EFFICIENCY RED
IPD2545A
GREEN
IPD2547A
YELLOW
IPD2548A
0.252" 4-Character 5 x 7 Dot Matrix X-Y Stackable
Industrial Alphanumeric Programmable DisplayTM
with Built-in CMOS Control Functions
FEATURES
Four 0.252" Dot Matrix Characters in Hermetic
Package
Built-in Memory, Decoders, Multiplexer
and Drivers
Viewing Angle, X axis 40
, Y axis 75
128 Character ASCII Format (Upper and Lower
Case Characters)
Rugged Ceramic Package, Hermetic Sealed
Flat Glass Window
Wide Temperature Operating Range for Industrial
Use, 55
C to +100
C
8-bit Bidirectional Data BUS
READ/WRITE Capability
Built-in Character Generator ROM
TTL Compatible
Easily Cascaded for Multidisplay Operation
Less CPU Time Required
Software Controlled Features:
Programmable Highlight Attribute
(Blinking, Non-Blinking)
Asynchronous Memory Clear Function
Lamp Test
Display Blank Function
Single or Multiple Character Blinking
Function
Three Programmable Brightness Levels
DESCRIPTION
The IPD2545A (high efficiency red), IPD2547A (green), and IPD2548A
(yellow) are four digit, High Reliability/Industrial, dot matrix, Program-
mable Displays that are aimed at satisfying the most demanding
industrial display requirements.
They are designed for use in harsh environments. The devices are
constructed in a hermetic package using four 0.25-inch high 5 x 7 dot
matrix displays.
The devices incorporate the latest in CMOS technology which is the
heart of the device intelligence. The CMOS controller chip is controlled
by a user supplied eight bit data word on the bidirectional BUS. The
ASCII data and attribute data are word driven. This approach allows
the IPD254XA to interface using the same techniques as a micropro-
cessor peripheral.
Applications include: control panels, night viewing applications (red
light), cockpit monitors, night vision goggle viewable displays (green),
portable and vehicle technology as well as industrial controllers.
.50
(12.70)
.252
(6.40)
.18 typ. (4.57)
.17 (4.32)
EIA Data Code
Intensity Code
1.200 max.
(30.48)
.490 max.
(12.45)
pin 1
indicator
.19
(4.83)
.150 ref.
(3.81)
.10 typ. (2.54)
.020 x .010 typ.
(.508 x .254)
.150 ref.
(3.81)
.300
typ.
(7.62)
part no.
pin 1.
OSRAM
YYWW Z
.170
typ.
(4.32)
Tolerance:
.XX=.01 (.254)
.XXX=.005 (.127)
Dimensions in inches (mm)
2001 OSRAM Opto Semiconductors Inc. San Jose, CA
IPD2545A/7A/8A
www.infineon.com/opto 408-456-4000
OSRAM Opto Semiconductors GmbH & Co. OHG Regensburg, Germany
www.osram-os.com +49-941-202-7178
2
July 5, 2001-14
Maximum Ratings
DC Supply Voltage ............................................ 0.5 to +6.0 Vdc
Input Voltage Relative to Ground
(all inputs)............................................... 0.5 to
V
CC
+0.5 Vdc
Operating Temperature .....................................55
C to 100
C
Storage Temperature..........................................65
C to 125
C
Thermal Resistance (
JC
)................................................ 30
C/W
Important:
Refer to Appnote 18, "Using and Handling Intelligent Displays". Since
this is a CMOS device, normal precautions should be taken to avoid
static damage.
Figure 1. Top View
Pin Assignments
1
RD
Read
11
WR
Write
2
CLK I/O
Clock I/O
12
D7
Data MSB
3
CLKSEL
Clock Select
13
D6
Data
4
RST
Reset
14
D5
Data
5
CE1
Chip Enable
15
D4
Data
6
CE0
Chip Enable
16
D3
Data
7
A2
Address MSB 17
D2
Data
8
A1
Address
18
D1
Data
9
A0
Address LSB
19
D0
Data LSB
10
GND
--
20
V
CC
--
DIGIT 3 DIGIT 2 DIGIT 1 DIGIT 0
Pin 1
20
10
11
Figure 2. Timing Characteristics--Data "Write" Cycle
Figure 3. Timing Characteristics--Data "Read" Cycle
Notes:
1. All input voltages are
V
IL
=0.8 V,
V
IH
=2.0 V.
2. These waveforms are not edge triggered.
TDS
TDH
TW
TACC
TAH
TAS
TCEH
TCES
2.0 V
0.8 V
CE0,
CE1
A0, A1
RD
2.0 V
0.8 V
2.0 V
0.8 V
2.0 V
0.8 V
D0D6
2.0 V
0.8 V
TRS
TRH
WR
*
*
*
*
*
T
DD
T
R
T
AH
T
AS
T
CEH
T
CES
2.0 V
0.8 V
CE0,
CE1
A0A3
T
RACC
2.0 V
0.8 V
2.0 V
0.8 V
2.0 V
0.8 V
D0D6
2.0 V
0.8 V
T
WS
T
WH
WR
RD
T
DH
T
RI
*
*
*
*
DATA OUT
*
DC Characteristics
Parameter
55
C
+25
C
+100
C
Units
Condition
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
I
CC
Blank
--
4.0
10
--
2.0
5.0
--
1.0
2.5
mA
V
CC
=5.0 V
(A
2
=1
all other inputs low)
I
CC
--
220
250
--
160
190
--
125
160
mA
V
CC
=5.0 V, 20 dots/digit,
(100% brightness)
I
IL
(all inputs)
--
70
120
--
60
100
--
50
80
A
V
CC
=5.0 V,
V
IH
=0.8 V
V
IH
(all inputs)
2.0
--
--
2.0
--
--
2.0
--
--
V
V
CC
=5.0 V 0.5 V
V
IL
(all inputs)
--
--
0.8
--
--
0.8
--
--
0.8
V
V
CC
=5.0 V 0.5 V
2001 OSRAM Opto Semiconductors Inc. San Jose, CA
IPD2545A/7A/8A
www.infineon.com/opto 408-456-4000
OSRAM Opto Semiconductors GmbH & Co. OHG Regensburg, Germany
www.osram-os.com +49-941-202-7178
3
July 5, 2001-14
Optical Characteristics
High Efficiency Red IPD2545A
High Efficiency Green IPD2547A
Yellow IPD2548A
Notes:
1)
The displays are categorized for luminous intensity with the intensity category designated by a letter code on the bottom of the package.
2)
Dominant wavelength
dom
is derived from the CIE chromaticity diagram and represents the single wavelength which defines the
color of the device.
3)
The luminous stearance of the LED may be calculated using the following relationships.
L
V
(cd/m
2
) =
I
V
(Candela)/A (Meter)
2
L
V
(Footlamberts) =
I
V
(Candela)/A (Foot)
2
A=8.4 x 10
7
ft
2
, 7.8 x 10
8
m
2
4)
All typical values specified at
V
CC
=5.0 V and
T
A
=25
C unless otherwise noted.
Description
Symbol
Min.
Typ.
(4)
Units
Test Condition
Peak Luminous Intensity per LED
(1,3)
(Character Average)
I
V
ave
75
150
cd
V
CC
=5.0 V, # sign "ON" on all digits at
full brightness,
T
A
=25
C
Peak Wavelength
peak
--
635
nm
--
Dominant Wavelength
(2)
dom
--
626
nm
--
Description
Symbol
Min.
Typ.
(4)
Units
Test Condition
Peak Luminous Intensity per LED
(1,3)
(Character Average)
I
V
ave
75
150
cd
V
CC
=5.0 V, # sign "ON" on all digits at
full brightness,
T
A
=25
C
Peak Wavelength
peak
--
568
nm
--
Dominant Wavelength
(2)
dom
--
574
nm
--
Description
Symbol
Min.
Typ.
(4)
Units
Test Condition
Peak Luminous Intensity per LED
(1,3)
(Character Average)
I
V
ave
75
150
cd
V
CC
=5.0 V, # sign "ON" on all digits at
full brightness,
T
A
=25
C
Peak Wavelength
peak
--
585
nm
--
Dominant Wavelength
(2)
dom
--
590
nm
--
Pin Definitions
Pin
Function
Definition
1
RD
Active low, will enable a processor to read
all registers.
2
CLK I/O
If CLK SEL (pin 3) is low, then expect an
external clock source into this pin. If CLK
SEL is high, then this pin will be the master
or source for all other devices which have
CLK SEL low.
3
CLKSEL
CLocK SELect determines the action of pin
2, CLK I/O. See section on Cascading for an
example.
4
RST
Reset. The Reset pulse should be less than
1 ms. Reset is used only to synchronize
blinking and will not clear the display.
5
CE1
Chip enable (active high).
6
CE0
Chip enable (active low).
7
A2
Address input (MSB).
8
A1
Address input.
Pin Definitions
(continued)
Pin
Function
Definition
9
A0
Address input (LSB).
10
GND
Ground.
11
WR
Write. Active low. If the device is selected,
a low on the write input loads the data into
memory.
12
D7
Data Bus bit 7 (MSB).
13
D6
Data Bus bit 6.
14
D5
Data Bus bit 5.
15
D4
Data Bus bit 4.
16
D3
Data Bus bit 3.
17
D2
Data Bus bit 2.
18
D1
Data Bus bit 1.
19
D0
Data Bus bit 0 (LSB).
20
V
CC
Positive power pin.
2001 OSRAM Opto Semiconductors Inc. San Jose, CA
IPD2545A/7A/8A
www.infineon.com/opto 408-456-4000
OSRAM Opto Semiconductors GmbH & Co. OHG Regensburg, Germany
www.osram-os.com +49-941-202-7178
4
July 5, 2001-14
Switching Specifications
(
V
CC
=4.5 V)
Switching specifications (V
CC
=4.5 V)
Notes:
1)
Wait 1.0
s between any Reads or Writes after writing a Control Word with a Clear (D7=1). Wait 1.0
s
between any Reads or Writes after Clearing a Control Word with a Clear (D7=0). All other Reads and
Writes can be back to back.
2)
All input voltages are (V
IL
=0.8 V, V
IH
=2.0 V)
3)
Data out voltages are measured with 100 pF on the data bus and the ability to source = 40
A and
sink=1.6 mA The rise and fall times are 60 ns. V
OL
=0.4 V, V
OH
=2.4 V.
Write Cycle Timing
Parameter
Description
Specification Minimum
55
C
+25
C
+100
C
Units
T
CLR
(1)
Clear
RAM
1.0
1.0
1.0
s
T
CLRD
(1)
Clear RAM Disable
1.0
1.0
1.0
s
T
AS
Address Setup
10
10
10
ns
T
CES
Chip Enable Setup
0
0
0
ns
T
RS
Read Enable Setup
10
10
10
ns
T
DS
Data Setup
20
30
50
ns
T
W
Write Pulse
60
70
90
ns
T
AH
Address
Hold
20
30
40
ns
T
DH
Data Hold
20
30
40
ns
T
CEH
Chip Enable Hold
0
0
0
ns
T
RH
Read Enable Hold
20
30
40
ns
T
ACC
Total Access Time = Setup Time + Write
Time + Hold Time
90
110
140
ns
Read Cycle Timing
Parameter
Description
Specification Minimum
55
C
+25
C
+100
C
Units
T
AS
Address
Setup
0
0
0
ns
T
CES
Chip Enable
0
0
0
ns
T
WS
Write Enable Setup
20
30
40
ns
T
DD
Data Delay Time
100
150
175
ns
T
R
Read Pulse
150
175
200
ns
T
AH
Address
Hold
0
0
0
ns
T
DH
Data Hold
0
0
0
ns
T
TRI
Time to Tristate (Max. time)
30
40
50
ns
T
CEH
Chip Enable Hold
0
0
0
ns
T
WH
Write Enable Hold
30
40
50
ns
T
RACC
Total Access Time = Setup Time + Read
Time + Time to Tristate
200
245
290
ns
T
WAIT
(1)
Wait Time between Reads
0
0
0
ns
2001 OSRAM Opto Semiconductors Inc. San Jose, CA
IPD2545A/7A/8A
www.infineon.com/opto 408-456-4000
OSRAM Opto Semiconductors GmbH & Co. OHG Regensburg, Germany
www.osram-os.com +49-941-202-7178
5
July 5, 2001-14
Figure 4. Block Diagram
Functional Description
The block diagram (Figure 4) includes 5 major blocks and inter-
nal registers (indicated by dotted lines).
Display Memory consists of a 5 x 8 bit RAM block. Each of the
four 8-bit words holds the 7-bits of ASCII data (bits D0D6) and
an attribute select bit (Bit D7). The fifth 8-bit memory word is
used as a control word register. A detailed description of the
control register and its functions can be found under the head-
ing Control Word. Each 8-bit word is addressable and can be
read from or written to.
Mode Selection
0=Low logic level, 1=High logic level, X=Don't care
Data Input Commands
CEO
CE1
RD
WR
Operation
0
1
0
0
None
1
X
X
X
None
X
0
X
X
None
X
X
1
1
None
CEO
CE1
RD
WR
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Operation
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
No Change
0
1
0
1
1
0
0
X
X
X
X
X
X
X
X
Read Digit 0 Data to Bus
0
1
1
0
1
0
0
0
0
1
0
0
1
0
0
($) Written to Digit 0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
(W) Written to Digit 1
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
(f) Written to Digit 2
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
(3) Written to Digit 3
0
1
1
0
1
0
0
1
X
X
X
X
X
X
X
Char. Written to Digit 0
and Cursor Enabled
Display Memory
(RAM) 4x8
Output
Control
Logic
Control
Reg
1x8
128 Char
ROM
Decode
and
Mux
Output
Latch
OSC
Logic
Display
Multiplexer
Column
Drivers
Row
Drivers
Display
D0-D7
CE0,CE1
A0-A2
RD, WR
CLK SEL
XCLK
RST
20
3
3
5
8
14
1
15
1
7
3
20
4
8
The Control Logic dictates all of the features of the display
device and is discussed in the Control Word section of this
data sheet.
The Character Generator converts the 7-bit ASCII data into the
proper dot pattern for the 128 characters shown in the charac-
ter set chart.
The Clock Source can originate either from the internal oscillator
clock or from an external sourceusually from the output of
another IPD2545/7/8A in a multiple module display.
The Display Multiplexer controls all display output to the digit
drivers so no additional logic is required for a display system.
The Column Drivers are connected directly to the display.
The Display has four digits. Each of the four digits is comprised
of 35 LEDs in a 5 x 7 dot array which makes up the alphanu-
meric characters.
The intensity of the display can be varied by the Control Word in
steps of 0% (Blank), 25%, 50%, and full brightness.
The Reset pin when activated clears the internal counter. A reset is
usually done after power up and is of very short duration-nanosec-
onds or microseconds. If the reset pin is held low for a longer time
(milliseconds) some or all LEDs in the bottom row may light up.
The appearance of lit LEDs during a "reset" is not an indication of a
malfunctioning part. It is advisable to keep the reset pulse as short
as possible to avoid displaying a row of lit LEDs.
Microprocessor Interface
The interface to the microprocessor is through the address lines.
(A0A2), the data bus (D0D7), two chip select lines (CE0, CE1),
and read (RD) and write (WR) lines.
The CE0 should be held low when executing a read, or write
operation. CE1 must be held high.
The read and write lines are both active low. During a valid read
the data lines (D0D7) become outputs. A valid write will enable
the data lines as inputs.
Input Buffering
If a cable length of 6 inches or more is used, all inputs to the dis-
play should be buffered with a tri-state non-inverting buffer
mounted as close to the display as conveniently possible. Recom-
mended buffers are: 74LS245 for the data lines and 74LS244 for
the control lines.
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