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Электронный компонент: 4305-02

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Page 1 of 11
Document No. 70/0159~02C
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
4x4mm -20 Lead QFN
The PE4305 is a high linearity, 5-bit RF Digital Step Attenuator
(DSA) covering a 15.5 dB attenuation range in 0.5 dB steps,
and is pin compatible with the PE430x series. This 50-ohm RF
DSA provides both parallel (latched or direct mode) and serial
CMOS control interface, operates on a single 3-volt supply and
maintains high attenuation accuracy over frequency and
temperature. It also has a unique control interface that allows
the user to select an initial attenuation state at power-up. The
PE4305 exhibits very low insertion loss and low power
consumption. This functionality is delivered in a 4x4 mm QFN
footprint.

The PE4305 is manufactured in Peregrine's patented Ultra
Thin Silicon (UTSi) CMOS process, offering the performance
of GaAs with the economy and integration
of conventional
CMOS.
Product Specification
50
RF Digital Attenuator
5-bit, 15.5 dB, DC 4.0 GHz
Product Description
Figure 1. Functional Schematic Diagram
PE4305
Features
Attenuation: 0.5 dB steps to 15.5 dB
Flexible parallel and serial programming
interfaces
Latched or direct mode
Unique power-up state selection
Positive CMOS control logic
High attenuation accuracy and linearity
over temperature and frequency
Very low power consumption
Single-supply operation
50
impedance
Pin compatible with PE430x series
Packaged in a 20 Lead 4x4 mm QFN
Control Logic Interface
Parallel Control
Power-Up Control
Serial Control
RF Input
RF Output
Switched Attenuator Array
6
3
2
Figure 2. Package Type
Table 1. Electrical Specifications @ +25C, V
DD
= 3.0 V
Notes: 1. Device Linearity will begin to degrade below 1Mhz
2. See Max input rating in Table 2 & Figures on Pages 2 to 4 for data across frequency.
3. Note Absolute Maximum in Table 3.
Parameter Test
Conditions
Frequency
Minimum
Typical Maximum Units
Operation Frequency
DC
4000
MHz
Insertion Loss
2
DC - 2.2 GHz
-
1.5
2.25
dB
Attenuation Accuracy
Any Bit or Bit
Combination
DC - 2.2 GHz
- -
(0.25 + 3% of atten setting)
not to exceed 0.4 dB
dB
1 dB Compression
3
1 MHz - 2.2 GHz
30
34
-
dBm
Input IP3
1, 2
Two-tone inputs
+18 dBm
1 MHz - 2.2 GHz
-
52
-
dBm
Return Loss
DC - 2.2 GHz
15
20
- dB
Switching Speed
50% control to 0.5 dB
of final value
- -
1
s
Product Specification
PE4305
Page 2 of 11
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70/0159~02C
UltraCMOSTM RFIC Solutions
Typical Performance Data (25C, V
DD
=3.0 V)
Figure 4. Attenuation at Major steps
Figure 6. Output Return Loss at Major
Attenuation Steps
Figure 5. Input Return Loss at Major
Attenuation
Steps
Figure 3. Insertion Loss
-5
-4
-3
-2
-1
0
0
500
1000
1500
2000
2500
3000
3500
4000
insertion loss @ 25 C
insertion loss @ -40 C
insertion loss @ 85 C
In
se
r
t
i
o
n
L
o
ss (d
B
)
Frequency (MHz)
0
5
10
15
20
0
500
1000
1500
2000
2500
3000
3500
4000
N
o
r
m
a
l
i
z
e
d
At
ten
uat
i
o
n (
d
B
)
Frequency (MHz)
15.5 dB
8 dB
4 dB
2 dB
1 dB
.5 dB
-50
-40
-30
-20
-10
0
0
500
1000
1500
2000
2500
3000
3500
4000
S1
1 (
d
B
)
Frequency (MHz)
15.5 dB
8 dB
-50
-40
-30
-20
-10
0
0
500
1000
1500
2000
2500
3000
3500
4000
S2
2 (
d
B
)
Frequency (MHz)
15.5 dB
Product Specification
PE4305
Page 3 of 11
Document No. 70/0159~02C
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Figure 8. Attenuation Error Vs. Attenuation
Setting at 10 MHz and 510 MHz
Figure 10. Attenuation Error Vs. Attenuation
Setting at
1510
MHz and 2010 MHz
Figure 9. Attenuation Error Vs. Attenuation
Setting 1010 MHz and 1210 MHz
Figure 7. Attenuation Error Vs. Frequency
Typical Performance Data (25C, V
DD
=3.0 V)
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0
500
1000
1500
2000
2500
3000
3500
4000
E
rro
r (
d
B
)
Frequency (MHz)
15.5 dB
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0
2
4
6
8
10
12
14
16
10 MHz @ 25 C
510 MHz @ 25 C
10 MHz @ -40 C
510 MHz @ -40 C
10 MHz @ 85 C
510 MHz @ 85 C
E
rro
r (
d
B
)
Attenuation State (dB)
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0
2
4
6
8
10
12
14
16
1010 MHz @ 25 C
1010 MHz @ -40 C
1010 MHz @ 85 C
1210 MHZ @ 25 C
1210 MHz @ -40 C
1210 MHz @ 85 C
E
r
ror (
d
B
)
Attenuation State (dB)
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0
2
4
6
8
10
12
14
16
1510 MHz @ 25 C
1510 MHz @ -40 C
1510 MHz @ 85 C
2010 MHz @ 25 C
2010 MHz @ -40 C
2010 MHz @ 85 C
E
r
ror (
d
B
)
Attenuation State (dB)
Product Specification
PE4305
Page 4 of 11
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70/0159~02C
UltraCMOSTM RFIC Solutions
Figure 12. 1 dB Compression vs. Frequency
Figure 13. Input IP3 vs. Frequency
Figure 11. Attenuation Error vs. Attenuation
Setting at
2010 MHz and 2510 MHz
Typical Performance Data (25C, V
DD
=3.0 V)
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0
2
4
6
8
10
12
14
16
2010 MHz @ 25 C
2510 MHz @ 25 C
2010 MHz @ -40 C
2510 MHz @ -40 C
2010 MHz @ 85 C
2510 MHz @ 85 C
E
rro
r (
d
B
)
Attenuation State (dB)
20
25
30
35
40
1000
1500
2000
2500
3000
0 dB
0.5 dB
1 dB
2 dB
1
dB C
o
m
p
re
s
s
i
o
n (
d
Bm
)
Frequency (MHz)
20
25
30
35
40
45
50
55
60
500
1000
1500
2000
2500
3000
0 dB
0.5 dB
1 dB
2 dB
4 dB
8 dB
15.5 dB
IP
3
(
d
Bm)
Frequency (MHz)
Product Specification
PE4305
Page 5 of 11
Document No. 70/0159~02C
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Table 2. Pin Descriptions
Table 3. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
Table 4. DC Electrical Specifications
Note 1: Both RF ports must be held at 0 VDC or DC blocked with an
external series capacitor.
2: Latch Enable (LE) has an internal 100 k
resistor to VDD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to VSS (-VDD) to bypass and disable
internal negative voltage generator.
4. Place a 10 k
resistor in series, as close to pin as possible to
avoid frequency resonance. See "Resistor on Pin 3" paragraph.
Figure 14. Pin Configuration (Top View)
V
DD
PU
P1
PU
P2
V
DD
GND
1
20
19
18
17
16
15
14
13
12
11
6
7
8
9
10
2
3
4
5
C16
RF1
Data
Clock
LE
GND
Vss/GND
P/S
RF2
C8
C4
C2
GN
D
C1
C0
.
5
20-lead QFN
4x4mm
Exposed Solder Pad
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM
devices are immune to latch-up.
Switching Frequency
The PE4305 has a maximum 25 kHz switching
rate.
Resistor on Pin 3
A 10 k
resistor on the input to Pin 3 (see Figure
16) will eliminate package resonance between the
RF input pin and the digital input. Specified
attenuation error versus frequency performance is
dependent upon this condition.
Pin No.
Pin Name
Description
1
N/C
No connect. Can be connected to any
bias.
2
RF1
RF port (Note 1).
3
Data
Serial interface data input (Note 4).
4
Clock
Serial interface clock input.
5
LE
Latch Enable input (Note 2).
6 V
DD
Power supply pin.
7
N/C
No connect. Can be connected to any
bias.
8
PUP2
Power-up selection bit.
9 V
DD
Power supply pin.
10 GND
Ground
connection.
11 GND
Ground
connection.
12 V
ss
/GND
Negative supply voltage or GND
connection(Note 3)
13
P/S
Parallel/Serial mode select.
14
RF2
RF port (Note 1).
15
C8
Attenuation control bit, 8 dB.
16
C4
Attenuation control bit, 4 dB.
17
C2
Attenuation control bit, 2 dB.
18 GND
Ground
connection.
19
C1
Attenuation control bit, 1 dB.
20
C0.5
Attenuation control bit, 0.5 dB.
Paddle
GND
Ground for proper operation
Symbol Parameter/Conditions Min Max Units
V
DD
Power
supply
voltage
-0.3
4.0 V
V
I
Voltage on any input
-0.3
V
DD
+
0.3
V
T
ST
Storage temperature range
-65
150
C
T
OP
Operating temperature
range
-40 85 C
P
IN
Input power (50
)
24
dBm
V
ESD
ESD voltage (Human Body
Model)
500
V
Parameter Min
Typ
Max
Units
V
DD
Power Supply Voltage
2.7
3.0
3.3
V
I
DD
Power Supply Current
100
A
Digital Input High
0.7xV
DD
V
Digital Input Low
0.3xV
DD
V
Digital Input Leakage
1
A