Page 1 of 8
Document No. 70-0106-03
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
V
DD
= 3.0 V, -40 C
T
A
85 C,
unless otherwise specified
The PE3511 is a high-performance static
UltraCMOSTM
prescaler with a fixed divide ratio of 2. Its operating frequency
range is DC to 1500 MHz. The PE3511 operates on a nominal
3 V supply and draws only 8 mA. The input and output
interfaces support both AC-coupled, low-Z RF as well as direct
connection to low voltage positive logic devices. It is packaged
in a small 6-lead SC-70 and is ideal for frequency scaling
solutions
The PE3511 is manufactured in Peregrine's patented Ultra
Thin Silicon (UTSi) CMOS process, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Product Specification
1500 MHz Low Power UltraCMOSTM
Divide-by-2 Prescaler
Product Description
Figure 1. Functional Schematic Diagram
PE3511
Features
DC to 1500 MHz operation
Fixed divide ratio of 2
Low-power consumption: 8 mA typical
@ 3V
RF or LV Digital Interface
Ultra-small package: 6-lead SC-
70
Table 1. Electrical Specifications (Z
S
= Z
L
= 50
)
Figure 2. Package Type
6-lead SC70
PREAMP
DRIVER
OUTPUT BUFFER
D Q
CLK
QB
IN
OUT
Parameter Conditions
Minimum
Typical
Maximum
Units
Supply Voltage
2.85
3.0
3.15
V
Supply Current
8
12
mA
Input Frequency (F
in
)
DC
1500
MHz
Input Power (P
in
)
DC <
Fin
1000 MHz
-10
+10
dBm
1000 MHz < Fin
1500
0
dBm
Output Power (P
out
)
DC < Fin
1500 MHz
2
dBm
Product Specification
PE3511
Page 2 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0106-03
UltraCMOSTM RFIC Solutions
Table 2. DC Electrical Characteristics (-40 C
T
A
85 C)
Symbol
Parameter
Condition
Typical
Unit
V
IH
High Level Input Voltage
2.7 V V
DD
3.3 V
2.0
V
V
IL
Low Level Input Voltage
2.7 V V
DD
3.3 V
0.8
V
V
OH
High Level Output Voltage
V
DD
= 2.7 V; I
OH
= 2.9 mA
2.2
V
V
OL
Low Level Output Voltage
V
DD
= 2.7 V; I
OL
= 2.6 mA
0.4
V
Symbol
Parameter
Condition*
Typical
Unit
t
PHL
Propagation Delay
(High to Low)
50 MHz Pulse Train Input;
C
L
= 10 pF, R
L
= 500
2.6
ns
t
PLH
Propagation Delay
(Low to High)
50 MHz Pulse Train Input;
C
L
= 10 pF, R
L
= 500
2.8
ns
t
r
Output Rise Time
(10% to 90%)
50 MHz Pulse Train Input;
C
L
= 10 pF, R
L
= 500
2.2
ns
t
f
Output Fall Time
(90% to 10%)
50 MHz Pulse Train Input;
C
L
= 10 pF, R
L
= 500
2.1
ns
Frequency
Condition
Typical
Unit
50 MHz
200 mVp-p Sinusoidal Input;
C
L
= 10 pF, R
L
= 500
2.3
Vp-p
500 MHz
200 mVp-p Sinusoidal Input;
C
L
= 10 pF, R
L
= 500
1.9
Vp-p
1500 MHz
200 mVp-p Sinusoidal Input;
C
L
= 10 pF, R
L
= 500
1.6
Vp-p
Table 3. AC Characteristics (-40 C
T
A
85 C)
Table 4. Typical Output Swing (V
DD
= 2.7 V)
* See figure 5 for AC test circuit
Product Specification
PE3511
Page 3 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0106-03
www.psemi.com
Table 5. Pin Descriptions
Table 6. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 6.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM
devices are immune to latch-up.
Figure 3. Pin Configuration (Top View)
Device Functional Considerations
The PE3511 divides an input signal, up to a
frequency of 1500 MHz, by a factor of two thereby
producing an output frequency at half the input
frequency. To work properly with low impedance,
ground referenced interfaces, the input and output
signals (pins 3 & 6) must be AC coupled via an
external capacitor, as shown in the test circuit in
Figure 4.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 9 for a layout example.
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage. Exposure
to absolute maximum ratings for extended periods
may affect device reliability.
.
511
1
2
3
4
5
6
OUT
GND
V
DD
NC
GND
IN
pin 1
SC-70
Pin
No.
Pin
Name
Description
1
N/C
No Connect. This pin should be left open.
2
GND
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
3
IN
Input signal pin. DC blocking capacitor
required (100 pF typical).
4 V
DD
Power supply pin. Bypassing is required.
5 GND
Ground
pin.
6
OUT
Divided frequency output pin. DC blocking
capacitor required (100 pF typical).
Symbol Parameter/Conditions Min Max Units
V
DD
Supply voltage
4.0
V
P
in
Input
Power
13 dBm
T
ST
Storage temperature range
-65
150
C
T
OP
Operating
temperature
range
-40 85 C
VESD
ESD voltage (Human Body
Model)
2000
V
Product Specification
PE3511
Page 4 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0106-03
UltraCMOSTM RFIC Solutions
Figure 4. Test Circuit Block Diagram
Figure 5. AC Test Circuit
GND
IN
VDD
GND
OUT
N/C
1
2
3
4
5
6
PE3511
50 Ohm
100 pF
100 pF
1000 pF
VDD
3V +/- 0.15 V
100 pF
50 Ohm
Spectrum
Analyzer
Signal
Generator
PE3511
Pulse
Generator
R
L
C
L
R
T
V
DD
R
T =
Zout of pulse generator
(usually 50 ohm)
Product Specification
PE3511
Page 5 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0106-03
www.psemi.com
Figure 6. Input Sensitivity
Figure 7. Device Current
Typical Performance Data: V
DD
= 3.0 V
Figure 8. Output Power
PDF 
ZIP