Document No. 70-0035-02
www.psemi.com
Page 1 of 13
2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Peregrine's PE9701 is a high-performance integer-N PLL
capable of frequency synthesis up to 3.0 GHz. The device
is designed for superior phase noise performance while
providing an order of magnitude reduction in current
consumption, when compared with existing commercial
space PLLs.
The PE9701 features a 10/11 dual modulus prescaler,
counters, and a phase comparator as shown in Figure 1.
Counter values are programmable through either a serial or
parallel interface and can also be directly hard wired.
The PE9701 is optimized for commercial space
applications. Single Event Latch up (SEL) is physically
impossible and Single Event Upset (SEU) is better than
10
-9
errors per bit / day.
It is manufactured on Peregrine's
UltraCMOSTM process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate, offering
excellent RF performance and intrinsic radiation tolerance.
Product Specification
3000 MHz UltraCMOSTM Integer-N PLL
Rad Hard for Space Applications
Product Description
PE9701
Features
3.0 GHz operation
10/11 dual modulus prescaler
Internal phase detector with charge
pump
Serial, parallel or hardwired
programmable
Ultra-low phase noise
SEU < 10
-9
errors / bit-day
100 Krad (Si) total dose
44-lead CQFJ
Figure 1. Block Diagram
F
in
F
in
Prescaler
10/11
20
Main
Counter
20
Secon-
dary
20-bit
Latch
20
Primary
20-bit
Latch
Pre_en
M(6:0)
A(3:0)
R(3:0)
16
20
R Counter
f
r
Phase
Detector
6
6
f
c
f
p
8
D(7:0)
13
Sdata
PD_U
PD_D
Charge
Pump
CP
Product Specification
PE9701
Page 2 of 13
2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0035-02
UltraCMOSTM RFIC Solutions
Table 1. Pin Descriptions
Figure 2. Pin Configurations (Top View)
44-lead CQFJ
Figure 3. Package Type
11
12
13
14
15
16
17
10
9
8
7
6
5
4
3
2
1 44 43 42 41 40
35
34
33
32
31
30
29
36
37
38
39
18 19 20 21 22 23 24 25 26 27 28
D
0
, M
0
D
1
, M
1
D
2
, M
2
D
3
, M
3
V
DD
V
DD
S_WR, D
4
, M
4
Sdata, D
5
, M
5
Sclk, D
6
, M
6
FSELS, D
7
, Pre_en
GND
GND
f
p
V
DD
_f
p
D
out
V
DD
C
ext
V
DD
CP
N/C
V
DD
_f
c
f
c
F
in
F
in
H
op_W
R
A_
W
R
M
1_W
R
V
DD
B
m
ode
S
m
ode,
A
3
M
2_W
R
,
A
2
E_
W
R
,
A
1
F
SEL
P,
A
0
GN
D
R
3
R
2
R
1
R
0
V
DD
En
h
LD
fr
GN
D
GN
D
Pin No.
Pin Name
Interface Mode
Type
Description
1
V
DD
ALL
(Note 1)
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
2
R
0
Direct
Input
R Counter bit0 (LSB).
3
R
1
Direct
Input
R Counter bit1.
4
R
2
Direct
Input
R Counter bit2.
5
R
3
Direct
Input
R Counter bit3.
6
GND
ALL
(Note 1)
Ground.
7
D
0
Parallel
Input
Parallel data bus bit0 (LSB).
M
0
Direct
Input
M Counter bit0 (LSB).
8
D
1
Parallel
Input
Parallel data bus bit1.
M
1
Direct
Input
M Counter bit1.
9
D
2
Parallel
Input
Parallel data bus bit2.
M
2
Direct
Input
M Counter bit2.
10
D
3
Parallel
Input
Parallel data bus bit3.
M
3
Direct
Input
M Counter bit3.
11
V
DD
ALL
(Note 1)
Same as pin 1.
12
V
DD
ALL
(Note 1)
Same as pin 1.
13
S_WR
Serial
Input
Serial load enable input. While S_WR is "low", Sdata can be serially clocked.
Primary register data is transferred to the secondary register on S_WR or Hop_WR
rising edge.
D
4
Parallel
Input
Parallel data bus bit4
M
4
Direct
Input
M Counter bit4
Product Specification
PE9701
Page 3 of 13
Document No. 70-0035-02
www.psemi.com
2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Table 1. Pin Descriptions (continued)
Pin No.
Pin Name
Interface Mode
Type
Description
14
Sdata
Serial
Input
Binary serial data input. Input data entered MSB first.
D
5
Parallel
Input
Parallel data bus bit5.
M
5
Direct
Input
M Counter bit5.
15
Sclk
Serial
Input
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR
"low") or the 8-bit enhancement register (E_WR "high") on the rising edge of Sclk.
D
6
Parallel
Input
Parallel data bus bit6.
M
6
Direct
Input
M Counter bit6.
16
FSELS
Serial
Input
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for
programming of internal counters while in Serial Interface Mode.
D
7
Parallel
Input
Parallel data bus bit7 (MSB).
Pre_en
Direct
Input
Prescaler enable, active "low". When "high", F
in
bypasses the prescaler.
17
GND
ALL
Ground.
18
FSELP
Parallel
Input
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for
programming of internal counters while in Parallel Interface Mode.
A
0
Direct
Input
A Counter bit0 (LSB).
19
E_WR
Serial
Input
Enhancement register write enable. While E_WR is "high", Sdata can be serially
clocked into the enhancement register on the rising edge of Sclk.
Parallel
Input
Enhancement register write. D[7:0] are latched into the enhancement register on the
rising edge of E_WR.
A
1
Direct
Input
A Counter bit1.
20
M2_WR
Parallel
Input
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising
edge of M2_WR.
A
2
Direct
Input
A Counter bit2.
21
Smode
Serial, Parallel
Input
Selects serial bus interface mode (
Bmode=0, Smode=1) or Parallel Interface Mode
(Bmode=0, Smode=0).
A
3
Direct
Input
A Counter bit3 (MSB).
22
Bmode
ALL
Input
Selects direct interface mode (
Bmode=1).
23
V
DD
ALL
(Note 1)
Same as pin 1.
24
M1_WR
Parallel
Input
M1 write. D[7:0] are latched into the primary register (
Pre_en, M[6:0]) on the rising
edge of M1_WR.
25
A_WR
Parallel
Input
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge
of A_WR.
26
Hop_WR
Serial, Parallel
Input
Hop write. The contents of the primary register are latched into the secondary
register on the rising edge of Hop_WR.
27
F
in
ALL
Input
Prescaler input from the VCO. 3.0 GHz max frequency.
28
F
in
ALL
Input
Prescaler complementary input. A bypass capacitor in series with a 51
resistor
should be placed as close as possible to this pin and be connected directly to the
ground plane.
29
GND
ALL
Ground.
30
f
p
ALL
Output
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding V
DD
pin 31.
Product Specification
PE9701
Page 4 of 13
2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0035-02
UltraCMOSTM RFIC Solutions
Table 1. Pin Descriptions (continued)
Note 1: V
DD
pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
V
DD
pins 31 and 38 are used to enable test modes and should be left floating.
Note 2: All digital input pins have 70 k
pull-down resistors to ground.
Pin No.
Pin Name
Interface Mode
Type
Description
31
V
DD
-f
p
ALL
(Note 1)
V
DD
for f
p
32
Dout
Serial, Parallel
Output
Data Out. The MSEL signal and the raw prescaler output are available on Dout
through enhancement register programming.
33
V
DD
ALL
(Note 1)
Same as pin 1.
34
Cext
ALL
Output
Logical "OR" of PD_U and PD_D terminated through an on chip, 2 k
series resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting
amplifier used for driving LD.
35
V
DD
ALL
(Note 1)
Same as pin 1.
36
CP
ALL
Output
Charge pump current is sourced for "up" when f
c
leads f
p
and sinked for "down"
when f
c
lags f
p
.
37
NC
ALL
No connection.
38
V
DD
-f
c
ALL
(Note 1)
V
DD
for f
c
39
f
c
ALL
Output
Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding V
DD
pin 38.
40
GND
ALL
Ground.
41
GND
ALL
Ground.
42
f
r
ALL
Input
Reference frequency input.
43
LD
ALL
Output,
OD
Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD is
high impedance, otherwise LD is a logic low ("0").
44
Enh
Serial, Parallel
Input
Enhancement mode. When asserted low ("0"), enhancement register bits are
functional.
Product Specification
PE9701
Page 5 of 13
Document No. 70-0035-02
www.psemi.com
2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Table 2. Absolute Maximum Ratings
Note 1: Periodically sampled, not 100% tested. Tested per MIL-
STD-883,
M3015
C2
Table 4. ESD Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM
devices are immune to latch-up.
Table 3. Operating Ratings
Table 5. DC Characteristics:
V
DD
= 3.0 V, -40 C < T
A
< 85 C, unless otherwise specified
Symbol Parameter/Conditions Min Max Units
V
DD
Supply
voltage
-0.3
4.0 V
V
I
Voltage on any input
-0.3
V
DD
+ 0.3
V
I
I
DC into any input
-10
+10
mA
I
O
DC into any output
-10
+10
mA
T
stg
Storage temperature
range
-65 150 C
Symbol Parameter/Conditions Min Max Units
V
DD
Supply
voltage
2.85
3.15 V
T
A
Operating ambient
temperature range
-40 85 C
Symbol Parameter/Conditions Level
Units
V
ESD
ESD voltage (Human Body
Model) Note 1
1000 V
Symbol Parameter
Conditions
Min
Typ
Max
Units
I
DD
Operational supply current;
Prescaler disabled
Prescaler enabled
V
DD
= 2.85 to 3.15 V
10
24
31
mA
mA
Digital Inputs: All except f
r
, F
in
,
F
in
V
IH
High level input voltage
V
DD
= 2.85 to 3.15 V
0.7 x V
DD
V
V
IL
Low level input voltage
V
DD
= 2.85 to 3.15 V
0.3 x V
DD
V
I
IH
High level input current
V
IH
= V
DD
= 3.15 V
+70
A
I
IL
Low level input current
V
IL
= 0, V
DD
= 3.15 V
-1
A
Reference Divider input: f
r
I
IHR
High level input current
V
IH
= V
DD
= 3.15 V
+100
A
I
ILR
Low level input current
V
IL
= 0, V
DD
= 3.15 V
-100
A
R0 Input: R
0
I
IHRO
High level input current
V
IH
= V
DD
= 3.15 V
+70
A
I
ILRO
Low level input current
V
IL
= 0, V
DD
= 3.15 V
-5
A
Counter and phase detector outputs: f
c
, f
p
.
V
OLD
Output
voltage
LOW
I
out
= 6 mA
0.4
V
V
OHD
Output voltage HIGH
I
out
= -3 mA
V
DD
- 0.4
V
Lock detect outputs: Cext, LD
V
OLC
Output voltage LOW, Cext
I
out
= 100 A
0.4
V
V
OHC
Output voltage HIGH, Cext
I
out
= -100 A
V
DD
- 0.4
V
V
OLLD
Output voltage LOW, LD
I
out
= 6 mA
0.4
V
Charge Pump output: CP
I
CP
- Source
Drive current
V
CP
= V
DD
/ 2
-2.6
-2
-1.4
mA
I
CP
Sink
Drive current
V
CP
= V
DD
/
2
1.4 2 2.6
mA
I
CPL
Leakage current
1.0 V < V
CP
< V
DD
1.0 V
-1
1
A
I
CP
Source
vs. I
CP
Sink
Sink vs. source mismatch
VCP = V
DD
/ 2,
T
A
= 25 C
25
%
I
CP
vs. V
CP
Output current magnitude variation vs. voltage
V < V
CP
< V
DD
1.0 V
T
A
= 25 C
25
%
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