PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 1 of 7
Product Description
Figure 1. Functional Schematic Diagram
D
QB
Q
CLK
D
QB
Q
CLK
Pre-Amp
Output
Buffer
IN
OUT
D
QB
Q
CLK
Figure 2. Package Type
6-lead
SC-70
Table 1. Electrical Specifications
(Z
S
= Z
L
= 50
)
V
DD
= 3.0 V, -40
C T
A
85
C,
unless otherwise specified
Parameter Conditions
Minimum
Typical
Maximum
Units
Supply
Voltage
2.85 3.0 3.15 V
Supply Current
8
12
mA
Input Frequency (F
in
) DC
1000
MHz
Input Power (P
in
)
DC ! Fin ! 1000MHz
-10 +10
dBm
Output Power (P
out
)
DC ! Fin ! 1000MHz
0
dBm
ADVANCED INFORMATION
PE3513
1000 MHz Low Power CMOS
Divide-by-8 Prescaler
Features
DC to 1000 MHz operation
Fixed divide ratio of 8
Low-power operation: 8 mA
typical @ 3 V
Ultra small package: 6-lead
SC-70
The PE3513 is a high-performance static CMOS
prescaler with a fixed divide ratio of 8. Its operating
frequency range is DC to 1000 MHz. The PE3513
operates on a nominal 3 V supply and draws only 8 mA.
It is packaged in a small 6-lead SC-70 and is ideal for
frequency scaling solutions.
The PE3513 is manufactured in Peregrine's patented
Ultra-Thin Silicon (UTSi
) CMOS process, offering the
performance of GaAs with the economy and integration
of conventional CMOS.
PE3513
Advanced Information
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0108~00A
|
UTSi CMOS RFIC SOLUTIONS
Page 2 of 7
Table 2. DC Electrical Characteristics (-40
C T
A
85
C)
Symbol Parameter
Condition Typical
Unit
V
IH
High Level Input Voltage
2.7 V VDD 3.3 V
2.0
V
V
IL
High Level Input Voltage
2.7 V VDD 3.3 V
0.8
V
V
OH
High Level Output Voltage
VDD = 2.7 V; I
OH
= 2.9 mA
2.2
V
V
OL
Low Level Output Voltage
VDD = 2.7 V; I
OL
= 2.6 mA
0.4
V
Table 3. AC Characteristics (-40
C T
A
85
C)
Symbol Parameter
Condition* Typical
Unit
t
PHL
Propagation Delay
(High to Low)
50 MHz Pulse Train Input;
C
L
= 10 pF, R
L
= 500
4.1
ns
t
PLH
Propagation Delay
(Low to High)
50 MHz Pulse Train Input;
C
L
= 10 pF, R
L
= 500
3.9
ns
t
r
Output Rise Time
(10% to 90%)
50 MHz Pulse Train Input;
C
L
= 10 pF, R
L
= 500
2.0
ns
t
f
Output Fall Time
(90% to 10%)
50 MHz Pulse Train Input;
C
L
= 10 pF, R
L
= 500
2.0
ns
* See figure 5 for AC test circuit
Table 4. Typical Output Swing (VDD = 2.7 V)
Frequency Condition Typical
Unit
50 MHz
200 mVp-p Sinusoidal Input;
C
L
= 10 pF, R
L
= 500
2.3 Vp-p
500 MHz
200 mVp-p Sinusoidal Input;
C
L
= 10 pF, R
L
= 500
2.3 Vp-p
1000 MHz
200 mVp-p Sinusoidal Input;
C
L
= 10 pF, R
L
= 500
2.2 Vp-p
PE3513
Advanced Information
PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 3 of 7
Figure 3. Pin Configuration
GND
IN
VDD
GND
OUT
N/C 1
2
3
4
5
6
PE3513
Table 5. Pin Descriptions
Pin
No.
Pin
Name
Description
1
N/C
No Connect. This pin should be left open.
2 GND
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
3 IN
Input signal pin. DC blocking capacitor
required (100 pF typical).
4
VDD
Power supply pin. Bypassing is required.
5 GND
Ground
pin.
6 OUT
Divided frequency output pin. DC blocking
capacitor required (100 pF typical).
Table 6. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
VDD Supply
voltage
4.0 V
P
in
Input
Power
10
dBm
T
ST
Storage
temperature
range
-65 150
C
T
OP
Operating
temperature
range
-40 85
C
VESD
ESD voltage (Human
Body Model)
250 V
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the
same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 5.
Latch-Up Avoidance
Unlike conventional CMOS devices, UTSi CMOS
devices are immune to latch-up.
Device Functional Considerations
The PE3513 divides an input signal, up to a
frequency of 1000 MHz, by a factor of eight
thereby producing an output frequency at one-
eighth the input frequency. To work properly, the
input and output signals (pins 3 & 6) must be AC
coupled via an external capacitor, as shown in the
test circuit in Figure 4.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 7 for a layout example.
PE3513
Advanced Information
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0108~00A
|
UTSi CMOS RFIC SOLUTIONS
Page 4 of 7
GND
IN
VDD
GND
OUT
N/C
1
2
3
4
5
6
PE3513
50 Ohm
100 pF
100 pF
1000 pF
VDD
3V +/- 0.15 V
100 pF
50 Ohm
Spectrum
Analyzer
Signal
Generator
PE3513
Pulse
Generator
R
L
C
L
R
T
V
DD
R
T =
Zout of pulse generator
(usually 50 ohm)
Figure 4. Test Circuit Block Diagram
Figure 5. AC Test Circuit
PE3513
Advanced Information
PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 5 of 7
GND
IN
VDD
GND
OUT
N/C
1
2
3
4
5
6
PE3513
C1
C2
C5
J3
J1
C2
J6
Figure 6. Evaluation Board Schematic Diagram
Figure 7. Evaluation Board Layout
Evaluation Kit Operation
The SC-70 Prescaler Evaluation Board was
designed to help customers evaluate the PE3513
divide-by-8 prescaler. On this board, the device
input (pin 3) is connected to connector J1 through a
50 transmission line. A series capacitor (C1)
provides the necessary DC block for the device
input. A value of 100 pF was used for this board
layout; other applications may require a different
value.
The device output (pin 6) is connector to connector
J3 through a 50 transmission lone. A series
capacitor (C5) provides the necessary DC block for
the device output. This capacitor value must be
chosen to have a low impedance at the desired
output frequency of the device. A value of 100 pF
was chosen for the evaluation board.
The board is constructed of a two-layer FR4
material with a total thickness of 0.031". The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide above
ground plane model with trace width of 0.030", trace
gaps of 0.007", dielectric thickness of 0.028", metal
thickness of 0.0014", and
r
of 4.4. Note that the
predominate mode of these transmission lines is
coplanar waveguide.
J6 provides DC power to the device via pin 4. Two
decoupling capacitors (100 pF, 1000 pF) are
included on this trace. It is the responsibility of the
customer to determine proper supply decoupling for
their design application.
Applications Support
If you have a problem with your evaluation kit or if
you have applications questions call (858) 455-0660
and ask for applications support. You may also
contact us by fax or e-mail:
Fax: (858) 455-0770
E-Mail: help@peregrine-semi.com
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