PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 1 of 6
Product Description
Figure 1. Functional Schematic Diagram
RF
LO
IF
180
o
Two-Way
Power
Divider
180
o
Two-Way
Power
Divider
Figure 2. Package Type
6-lead
MLPM
3 x 3 mm
4
5
6
3
2
1
Table 1. Electrical Specifications @ +25 C
Parameter Minimum
Typical Maximum Units
Frequency Range:
LO
RF
IF*
2050
1800
--
--
--
260
2250
2000
--
MHz
MHz
MHz
Conversion Loss**
7.5
dB
Isolation:
LO-RF
LO-IF
33
35
dB
dB
Input IP3
32
dBm
Input 1 dB Compression
22
dBm
*An IF frequency of 260 MHz is a nominal frequency. The IF frequency can be specified by the user as long as the RF and LO frequencies are within the
specified maximum and minimum.
**Conversion Loss includes loss of IF transformer (M/A COM ETK4-2T, nominal loss 0.7 dB at 260 MHz).
Test conditions unless otherwise noted: IF = 260 MHz, LO input drive = 17 dBm, RF input drive = 0 dBm.
ADVANCE INFORMATION
PE4123
High Linearity Quad MOSFET
Mixer For PCS & 3G BTS
Features
Integrated, single-ended RF & LO
interfaces
High linearity: +32 dBm, 1.9 GHz
(+17 dBm LO)
Low-conversion loss: 7.5 dB
(+17 dBm LO)
High isolation: Typical LO-IF at
35 dB, LO-RF at 33 dB
Optimized for high-side LO
injection
Packaged in a very small 6-lead
3x3mm MLPM
The PE4123 is a high linearity, passive Quad MOSFET
Mixer for PCS & 3G Base Station Receivers, exhibiting
high dynamic range performance over a broad LO drive
range of up to +20 dBm. This mixer integrates passive
matching networks to provide single-ended interfaces for
the RF and LO ports, eliminating the need for external
RF baluns or matching networks. The PE4123 is
optimized for frequency down-conversion using high-side
LO injection for PCS & 3G Base Station applications, and
is also suitable for up-conversion applications.
The PE4123 is manufactured in Peregrine's patented
Ultra-Thin Silicon (UTSi
) CMOS process, offering the
performance of GaAs with the economy and integration
of conventional CMOS.
PE4123
Advance Information
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0042~02A
|
UTSi CMOS RFIC SOLUTIONS
Page 2 of 6
Figure 3. Pin Configuration
PE4123
IF1
GND
RF
IF2
GND
LO
4
5
6
3
2
1
Table 2. Pin Descriptions
Pin
No.
Pin
Name
Description
1
IF1
IF differential output
2 GND
Ground
connections
for Mixer. Traces
should be physically short and connect
immediately to ground plane for best
performance. The exposed solder pad
must also be soldered to the ground plane
for best performance.
3
RF
RF Input
4
LO
LO Input
5 GND
Ground
connections
for Mixer. Traces
should be physically short and connect
immediately to ground plane for best
performance. The exposed solder pad
must also be soldered to the ground plane
for best performance.
6
IF2
IF differential output
Table 3. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
T
ST
Storage temperature
range
-65 150
C
T
OP
Operating temperature
range
-40 85
C
P
LO
LO input power
20
dBm
P
RF
RF input power
16
dBm
V
ESD
ESD Sensitive Device
250
V
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the same
precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified.
Latch-Up Avoidance
Unlike conventional CMOS devices, UTSi CMOS
devices are immune to latch-up.
PE4123
Advance Information
PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 3 of 6
LO
IF
RF
Eval
Board
Sig
Gen
Sig
Gen
Hybrid
Tee
3 dB
PA
Sig
Gen
3 dB
Spectrum
Analyzer
3 dB
6 dB
6 dB
4123
4
5
6
3
2
1
LO
RF
IF
T2
6-lead
MLPM
3 x 3 mm
Figure 4. Evaluation Board Schematic Diagram
T2, M/A-Com E-Series RF 4:1 Transformer, 2.0 1000 MHz, ETK4-2T
Figure 5. Evaluation Board Layout
Table 4. Bill of Materials
Reference
Value / Description
T2
M/A Com ETK4-2T
R1 0
U1
PE4123 MLP Mixer
J1, J2, J3
SMA Connector
Figure 6. Evaluation Board Testing Block Diagram, 2-Tone Setup
Pin 1
PE4123
Advance Information
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0042~02A
|
UTSi CMOS RFIC SOLUTIONS
Page 4 of 6
0
5
10
15
20
25
30
1800
1850
1900
1950
2000
1dB
Com
p
r
s
s
i
on (
d
B
m
)
Frequency (MHz)
-10
-8
-6
-4
-2
0
1800
1840
1880
1920
1960
2000
C
o
n
v
e
r
s
i
on Lo
s
s
(
d
B
)
Frequency (MHz)
0
10
20
30
40
1800
1850
1900
1950
2000
II
P
3
(
d
B
m
)
Frequency (MHz)
Typical Performance Plots @ +25 C
Figure 7. Conversion Loss
Figure 8. Input 1dB Compression
Figure 9. Input IP3
PE4123
Advance Information
PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 5 of 6
Figure 10. Package Drawing
6-lead MLPM
Table 5. Ordering Information
Order
Code
Part Marking
Description
Package
Shipping
Method
4123-01 4123
PE4123-06MLP3x3-12800F
6-lead
3x3 MLPM
12800 units / Canister
4123-02
4123
PE4123-06MLP3x3-3000C
6-lead 3x3 MLPM
3000 units / T&R
4123-00
4123-EK
PE4123-06ML3x3P-EK
Evaluation Board
1 / Box
EDGE OF PLASTIC BODY
THIS FEATURE
APPLIES TO
BOTH ENDS OF
THE PKG.
DETAIL A
EXPOSED SLUG/
HEAT SINK
EXPOSED METALIZED
FEATURE
0.17 MIN.
0.24 +0.20
-0.08
0.125
0.17
0.30
0.025
0.025
DETAIL B
(2X)
EXPOSED
6
5
3
BOTTOM VIEW
2
1
4
3
0.10
C A B
0.05
C
0.95
L
C
0.35 +0.08
-0.02
0.29 +0.16
-0.09
1.21 0.10
0.605 0.05
1.050.05
2.010.10
EXPOSED PAD
SEE DETAIL A
R0.127 TYP
0.20 MIN.
R 0.15 TYP
SEATING
PLANE
SIDE VIEW
TOP VIEW
- C -
0.100 C
0.080 C
0.70 0.05
0.20 0.05
0.90 0.10
0.0250.025
10+2
-10
DETAIL C
SEE DETAIL B
3
1
PIN 1
MARK
CL
CL
3.00
0.125
3.00
0.125
0.10 C
0.10 C
2
3
6
5
4
4
4
- A -
- B -
3 COPLANARITY APPLIES TO EXPOSED HEAT SLUG AS WELL AS THE TERMINALS.
4 PROFILE TOLERANCE APPLIES TO PLASTIC BODY ONLY.
1. DIMENSIONS AND TOLERANCES ARE PER ANSi Y14.5
2. DIMENSIONS ARE IN MILLIMETERS, ANGLES ARE IN DEGREES.
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