PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 1 of 7
Product Description
Figure 1. Functional Schematic Diagram
RF1
RF2
CTRL
75
Figure 2. Package Type
6-lead
MLPM
3 x 3 mm
4
5
6
3
2
1
Table 1. Electrical Specifications @ +25 C
(Z
S
= Z
L
= 75
)
Parameter Condition
Minimum
Typical
Maximum
Units
Operating Frequency
1
DC
1300 MHz
Operating Power
CTRL=1/CTRL=0
30/24
dBm
Insertion Loss
DC 50 MHz
1000 MHz
0.5
0.75
0.65
1.0
dB
Isolation
DC 50 MHz
1000 MHz
71
44
85
47
dB
Return Loss
DC - 1000 MHz
14
20
dB
Input 1 dB Compression
2,4
1000
MHz
30
33
dBm
Input IP2
2
1000
MHz
80
dBm
Input IP3
2
1000 MHz
50
dBm
Video Feedthrough
3
15
mV
pp
Switching
Time
2
s
Notes: 1. Device linearity will begin to degrade below 1 MHz.
2. Measured in a 50 system.
3. Measured with a 1 ns risetime, 0/3 V pulse and 500 MHz bandwidth.
4. Note Absolute Maximum ratings in Table 3.
PRODUCT SPECIFICATION
PE4240
SPST CATV MOSFET Switch
Features
75-ohm impedance switch
Non-reflective at RF1, open
reflective at RF2 when OFF
75-ohm (0.25 watt) termination
High isolation: 85 dB at 5 MHz,
47 dB at 1 GHz
Low insertion loss: 0.5 dB at
5 MHz, 0.75 dB at 1 GHz
High input IP2: >80 dBm
CMOS/TTL single-pin control
Single +3 volt supply operation
Extremely low bias: 33 A @ 3V
The PE4240 is a high-isolation MOSFET Switch
designed for CATV applications, covering a broad
frequency range from DC up to 1.3 GHz. This single-
supply SPST switch integrates a single-pin CMOS
control interface, and is non-reflective at port RF1 and
open reflective at port RF2 when commanded OFF. It
also provides low insertion loss with extremely low bias
requirements while operating on a single 3-volt supply.
In a typical CATV application, the high isolation PE4240
can replace bulky and expensive mechanical switches.
The PE4240 is manufactured in Peregrine's patented
Ultra Thin Silicon (UTSi
) CMOS process, offering the
performance of GaAs with the economy and integration
of conventional CMOS.
PE4240
Product Specification
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0067~02A
|
UTSi CMOS RFIC SOLUTIONS
Page 2 of 7
Figure 3. Pin Configuration (Top View)
Exposed
Solder Pad
(bottom side)
V
DD
GND
RF1
RF2
GND
CTRL
4
5
6
3
2
1
Table 2. Pin Descriptions
Pin
No.
Pin
Name
Description
1 V
DD
Nominal 3 V supply connection.
1
2 GND
Ground
connection.
3
3 RF1
RF port.
2
4 CTRL
CMOS or TTL logic level:
High = RF1 to RF2 signal path
Low = RF1 isolated from RF2
5 GND
Ground connection.
3
6 RF2
RF port.
2
Notes: 1. A bypass capacitor should be placed as close as possible to
the pin.
2. Both RF pins must be DC blocked by an external capacitor
or held at 0 V
DC
.
3. The exposed pad must be soldered to the ground plane for
proper switch performance.
Table 3. Absolute Maximum Ratings
Symbol Parameter/Condition Min
Max Unit
V
DD
Power supply voltage
-0.3
4.0
V
V
I
Voltage on CTRL input
-0.3
5.5
V
T
ST
Storage temperature
-65
150
C
T
OP
Operating temperature
-40
85
C
P
IN
Input power (50),
CTRL=1/CTRL=0
33/24
dBm
V
ESD
ESD voltage
(Human Body Model)
200 V
Table 4. DC Electrical Specifications @ 25
C
Parameter Min
Typ
Max
Unit
V
DD
Power Supply
2.7
3.0
3.3
V
I
DD
Power Supply Current
(V
DD
= 3V, V
CNTL
= 3V)
33
40
A
Control Voltage High
70% V
DD
5
V
Control Voltage Low
0
30% V
DD
V
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the same
precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified.
Latch-Up Avoidance
Unlike conventional CMOS devices, UTSi CMOS
devices are immune to latch-up.
Device Description
The PE4240 high isolation SPST CATV Switch is
designed to support CATV applications such as
premium channel service connect/disconnect switch
blocks. This function is typically performed by bulky
and expensive mechanical switches. The high
isolation characteristics (>44 dB at 1 GHz, 85 dB
at 5 MHz), high compression point, and an
integrated 75 (0.25 watt) input termination make
the PE4240 an ideal, low cost solution.
Figure 4. Typical Application Block Diagram
2-way
Splitter
Premium
Channel
Filter
PE4240
PE4240
CATVin
CATVout
Table 5. Truth Table
Control Voltage
Signal Path
CTRL = CMOS or TTL High
RF1 to RF2
CTRL = CMOS or TTL Low
RF1 isolated from RF2
The control logic input pin (CTRL) is typically driven
by a 3-volt CMOS logic level signal, and has a
threshold of 50% of V
DD
. For flexibility to support
systems that have 5-volt control logic drivers, the
control logic input has been designed to handle a 5-
volt logic HIGH signal. (A minimal current will be
sourced out of the V
DD
pin when the control logic
input voltage level exceeds V
DD.
)
PE4240
Product Specification
PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 3 of 7
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
0
200
400
600
800
1000
1200
I
n
se
r
t
i
o
n
L
o
ss
(
d
B
)
Frequency (MHz)
-40!C
25!C
85!C
-100
-80
-60
-40
-20
0
0
200
400
600
800
1000
1200
Is
o
l
a
t
i
o
n
(
d
B
)
Frequency (MHz)
20
30
40
50
60
20
30
40
50
60
0
200
400
600
800
1000
1200
II
P
3
(
d
B
m
)
1
d
B C
o
mp
r
e
s
s
i
o
n
Po
i
n
t
(
d
Bm)
Frequency (MHz)
IIP3
Input 1dB Compression
Typical Performance Data @ -40
C to 85 C (Unless Otherwise Noted)
(75-ohm impedance except as indicated)
Figure 5. Insertion Loss
Figure 6. Input 1 dB Compression Point & IIP3
(50-ohm system impedance)
Figure 7. Isolation
PE4240
Product Specification
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0067~02A
|
UTSi CMOS RFIC SOLUTIONS
Page 4 of 7
-30
-24
-18
-12
-6
0
0
200
400
600
800
1000
1200
Re
t
u
r
n
Lo
ss
(
d
B
)
Frequency (MHz)
-30
-25
-20
-15
-10
-5
0
0
200
400
600
800
1000
1200
Re
t
u
r
n
Lo
ss
(
d
B
)
Frequency (MHz)
-30
-25
-20
-15
-10
-5
0
0
200
400
600
800
1000
1200
R
e
tu
r
n
L
o
s
s
(
d
B
)
Frequency (MHz)
Typical Performance Data @ 25
C
(75-ohm impedance)
Figure 8. RF1 Return Loss (CTRL = High)
Figure 9. RF1 Return Loss (CTRL = Low)
Figure 10. RF2 Return Loss (CTRL = High)
PE4240
Product Specification
PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 5 of 7
Evaluation Kit Information
Evaluation Kit
The SPST Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4240 SPST switch. The RF1 port is connected
through a 75 transmission line to the top left
BNC connector, J1. The RF2 port is connected
through a 75 transmission line to the BNC
connector on the top right side of the board, J2. A
through transmission line connects BNC
connectors J3 and J4. This transmission line can
be used to estimate the loss of the PCB over the
environmental conditions being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031". The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide model with
trace width of 0.021", trace gaps of 0.030",
dielectric thickness of 0.028", metal thickness of
0.0021" and R of 4.3. Note that the predominate
mode for these transmission lines is coplanar
waveguide with a ground plane.
J5 provides a means for controlling DC and digital
inputs to the device. Starting from the lower left
pin, the second pin to the right (J5-3) is connected
to the device V
DD
input. The fourth pin to the right
(J5-7) is connected to the device CTRL input. A
decoupling capacitor (100 pF) is provided on both
traces. It is the responsibility of the customer to
determine proper supply decoupling for their
design application. Removing these components
from the evaluation board has not been shown to
degrade RF performance.
Figure 11. Evaluation Board Layouts
Figure 12. Evaluation Board Schematic
VDD
CTRL
RF1
GND
GND
RF2
100 pF
Optional
J1
J2
J3
J4
J5-7
100 pF
Optional
J5-3
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