1
PS8571A 12/11/02
Product Description
Pericom Semiconductor's PI3B series of logic circuits are produced
using the Company's advanced submicron CMOS technology,
achieving industry-leading performance.
The PI3B4010 is a 3.3V, 10- to 40-bit demultiplexing/multiplexing bus
switch. It is intended for multiple data or address muxing. Industry
leading advantages include a propagation delay of 300ps, resulting
from the 35-ohm channel resistance, and low I/O capacitance. The
A-port multiplexes to one of four or all outputs allowing a complete
bank of 10 bits to switch. The switch is bidirectional.
Product Features
R
ON
is 35 ohms max.
Standard Operating Temperature: 0C to +70C
Channel ON Capacitance: 15pF max.
V
CC
Operating Range: +3.0V to +3.6V
Fast switching time: 3ns max.
Package options include:
- 64-ball Thin Fine Pitch Ball Grid Array (TFBGA)
Applications
DDR DIMM bank switching
Expanded Block Diagram
Logic Block Diagram
3.3V, High-Bandwidth, 40:10-Bit
DDR Mux/Demux NanoSwitchTM
PI3B4010
A
0
10
10
10
10
10
10
10
10
10
10
0
B
0
1
B
0
2
B
0
3
B
0
A
1
0
B
1
1
B
1
2
B
1
3
B
1
A
2
0
B
2
1
B
2
2
B
2
3
B
2
A
3
0
B
3
1
B
3
2
B
3
3
B
3
A
4
0
B
4
1
B
4
2
B
4
3
B
4
A
5
0
B
5
1
B
5
2
B
5
3
B
5
A
6
0
B
6
1
B
6
2
B
6
3
B
6
A
7
0
B
7
1
B
7
2
B
7
3
B
7
A
8
0
B
8
1
B
8
2
B
8
3
B
8
A
9
SEL
0
0
B
9
1
B
9
2
B
9
3
B
9
SEL
1
SEL
2
SEL
3
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0B0
0B9
1B0
1B9
2B9
3B9
A 0
A 9
SEL0
SEL1
SEL2
SEL3
2B0
3B0
. . . . . .
. . . .
. . . .
. . . .
.
. . .
10
A
B
SEL
2
PS8571A 12/11/02
PI3B4010
3.3V, High Bandwidth, 40:10-Bit,
DDR Mux/Demux NanoSwitch
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1
2
3
4
5
6
7
8
9
10
11
A
NC
SEL
1
V
DD
1
B
0
2
B
0
3
B
0
2
B
1
3
B
1
0
B
2
B SEL
2
SEL
0
GND
0
B
0
Ao
0
B
1
1
B
1
A
1
GND
1
B
2
C
V
DD
SEL
3
A
2
2
B
2
D
GND
3
B
2
E
2
B
9
3
B
9
0
B
3
1
B
3
F
1
B
9
A
9
A
3
2
B
3
G
0
B
9
3
B
8
GND
3
B
3
H
2
B
8
0
B
4
J
1
B
8
A
8
A
4
1
B
4
K
0
B
8
GND
A
7
0
B
7
3
B
6
A
6
GND
3
B
5
A
5
3
B
4
2
B
4
L
3
B
7
2
B
7
1
B
NC = No Connection
7
2
B
6
1
B
6
0
B
6
2
B
5
1
B
5
0
B
5
Top View
NC
e
m
a
N
n
i
P
n
o
i
t
p
i
r
c
s
e
D
A
N
s
n
i
P
t
u
p
n
I
x
u
m
e
D
N
B
0
-
N
B
9
s
n
i
P
t
u
p
n
I
x
u
M
L
E
S
N
)
W
O
L
e
v
it
c
A
(
s
n
i
P
t
c
e
l
e
S
k
n
a
B
D
N
G
d
n
u
o
r
G
V
D
D
r
e
w
o
P
Note: N = 0 through 3 for each set of 10 Bits
Product Pin Description
Truth Table
n
o
i
t
c
n
u
F
L
E
S
0
L
E
S
1
L
E
S
2
L
E
S
3
A
t
c
e
n
n
o
C
N
o
t
0
B
N
L
H
H
H
A
t
c
e
n
n
o
C
N
o
t
1
B
N
H
L
H
H
A
t
c
e
n
n
o
C
N
o
t
2
B
N
H
H
L
H
A
t
c
e
n
n
o
C
N
o
t
3
B
N
H
H
H
L
0
B
N
,
1
B
N
,
2
B
N
,
3
B
N
,
n
w
o
d
ll
u
P
=
A
N
Z
-i
H
=
H
H
H
H
Product Pinout by Location on Connection Diagram
Storage Temperature .................................................. 65C to +150C
Supply Voltage Range ................................................ 0.5V to +4.6V
DC Input Voltage .......................................................... 0.5V to +4.6V
DC Output Current .................................................................... 120mA
Power Dissipation ........................................................................ 0.5W
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
3
PS8571A 12/11/02
PI3B4010
3.3V, High Bandwidth, 40:10-Bit,
DDR Mux/Demux NanoSwitch
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DC Electrical Characteristics over Operating Range
(T
A
= 0C to 70C, V
CC
= 3.3V 5%)
r
e
t
e
m
a
r
a
P
n
o
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t
p
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e
D
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t
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)
1
(
.
n
i
M
.
p
y
T
)
2
(
.
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M
s
t
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U
V
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tl
o
V
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t
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a
r
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G
6
.
1
V
C
C
3
.
0
+
V
V
L
I
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g
a
tl
o
V
W
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p
n
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l
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G
I
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d
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t
n
a
r
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G
3
.
0
9
.
0
V
K
I
e
g
a
tl
o
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e
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p
m
a
l
C
V
C
C
V
,.
x
a
M
=
N
I
=
A
m
8
1
7
.
0
2
.
1
I
H
I
t
n
e
r
r
u
C
H
G
I
H
t
u
p
n
I
V
C
C
V
,.
x
a
M
=
N
I
V
=
C
C
0
1
A
I
L
I
t
n
e
r
r
u
C
W
O
L
t
u
p
n
I
V
C
C
V
,.
x
a
M
=
N
I
D
N
G
=
0
1
R
N
O
e
c
n
a
t
s
i
s
e
R
n
O
h
c
ti
w
S
)
3
(
V
C
C
V
8
.
0
,.
n
i
M
=
V
N
I
I
,
V
5
.
2
N
I
A
m
0
2
=
5
2
5
3
R
)
N
O
(
T
A
L
F
s
s
e
n
t
a
l
F
e
c
n
a
t
s
i
s
e
R
n
O
)
4
(
V
C
C
V
,.
n
i
M
=
N
I
I
V
7
.
1
d
n
a
V
8
.
0
@
N
I
A
m
0
2
=
0
.
1
R
N
O
h
c
t
a
m
e
c
n
a
t
s
i
s
e
R
n
O
y
n
a
o
t
s
t
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p
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e
t
n
e
c
m
o
r
f
t
r
o
p
r
e
h
t
o
)
4
(
V
C
C
V
8
.
0
,.
n
i
M
=
V
N
I
I
,
V
5
.
2
N
I
A
m
0
2
=
9
.
0
2
R
D
P
e
c
n
a
t
s
i
s
e
R
n
w
o
D
-l
l
u
P
V
N
I
V
5
.
2
o
t
V
0
=
0
8
0
0
1
0
3
1
s
r
e
t
e
m
a
r
a
P
n
o
i
t
p
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t
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T
.
p
y
T
)
4
(
.
x
a
M
s
t
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C
N
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e
c
n
a
ti
c
a
p
a
C
t
u
p
n
I
V
N
I
V
0
=
5
.
3
F
p
C
)
A
(
F
F
O
F
F
O
h
c
ti
w
S
,
e
c
n
a
ti
c
a
p
a
C
A
t
r
o
P
0
.
2
1
C
)
B
/
A
(
N
O
N
O
h
c
ti
w
S
,
e
c
n
a
ti
c
a
p
a
C
B
/
A
0
.
5
1
C
)
B
(
F
F
O
F
F
O
h
c
ti
w
S
,
e
c
n
a
ti
c
a
p
a
C
B
t
r
o
P
5
.
4
Capacitance
(T
A
= 25C, f = 1 MHz)
Notes:
1. For min. or max. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, T
A
= 25C ambient and maximum loading.
3. Measured by the voltage drop between A and B pins at indicated current through the switch. ON resistance is determined by the
lower of the voltages on the two (A & B) pins.
4. This parameter is determined by device characterization but is not production tested.
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at V
CC
= 3.3V, +25C ambient.
3. Per TTL driven input (control inputs only); A and B pins do not contribute to I
CC
.
Power Supply Characteristics
s
r
e
t
e
m
a
r
a
P
n
o
i
t
p
i
r
c
s
e
D
s
n
o
i
t
i
d
n
o
C
t
s
e
T
)
1
(
.
n
i
M
.
p
y
T
)
2
(
.
x
a
M
s
t
i
n
U
I
C
C
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
t
n
e
c
s
i
u
Q
V
C
C
V
,.
x
a
M
=
N
I
V
r
o
D
N
G
=
C
C
0
1
A
4
PS8571A 12/11/02
PI3B4010
3.3V, High Bandwidth, 40:10-Bit,
DDR Mux/Demux NanoSwitch
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Switching Characteristics
(over operating range over recommended operating free-air temperature range).
r
e
t
e
m
a
r
a
P
n
o
i
t
p
i
r
c
s
e
D
s
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i
t
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d
n
o
C
m
o
C
s
t
i
n
U
.
n
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M
p
y
T
.
x
a
M
t
Y
I
y
a
l
e
D
n
o
it
a
g
a
p
o
r
P
)
3
,
2
(
A
N
B
o
t
N
Z
/
w
O
s
m
h
O
0
5
=
3
.
0
s
n
t
Y
S
L
E
S
-
e
m
i
T
t
c
e
l
e
S
s
u
B
N
A
o
t
N
B
,
N
5
.
0
0
.
3
t
L
Z
P
L
E
S
-
e
m
i
T
e
l
b
a
n
E
s
u
B
N
A
o
t
N
B
,
N
5
.
0
0
.
3
t
Z
L
P
L
E
S
-
e
m
i
T
e
l
b
a
s
i
D
s
u
B
N
A
o
t
N
B
,
N
5
.
0
0
.
3
t
)
o
(
K
S
A
(
s
t
r
o
p
r
e
t
n
e
c
n
e
e
w
t
e
b
w
e
k
s
t
u
p
t
u
O
4
A
&
5
t
r
o
p
r
e
h
t
o
y
n
a
o
t
)
)
2
(
1
.
0
2
.
0
t
)
p
(
K
S
(
t
u
p
t
u
o
e
m
a
s
e
h
t
f
o
s
n
o
it
i
s
n
a
r
t
e
ti
s
o
p
p
o
n
e
e
w
t
e
b
w
e
k
S
It
L
H
P
t
-
H
L
P
I)
)
2
(
1
.
0
2
.
0
Notes:
1. See test circuit and waveforms.
2. This parameter is guaranteed by design.
3. The bus switch contributes no propagational delay other than the RC delay of the ON resistance of the switch and the load
capacitance. The time constant for the switch alone is of the order of 0.75ns for 50pF load. Since this time constant is much smaller
than the rise/fall times of typical driving signals, it adds very little propagational delay to the system. Propagational delay of the
bus switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the
load on the driven side.
Notes:
1. C
L
= Load capacitance: includes jig and probe capacitance.
2. R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator
3. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
4. All input impulses are supplied by generators having the following characteristics: PRR
MHz, Z
O
= 50
, t
R
2.5ns, t
F
2.5ns.
5. The outputs are measured one at a time with one transition per measurement.
Test Circuits for All Outputs
(1)
t
s
e
T
h
c
t
i
w
S
)
e
d
i
s
A
n
o
t
u
p
t
u
o
(
W
O
L
e
l
b
a
n
E
,
W
O
L
e
l
b
a
s
i
D
V
0
.
5
)
e
d
i
s
A
n
o
t
u
p
t
u
o
(
H
G
I
H
e
l
b
a
n
E
,
H
G
I
H
e
l
b
a
s
i
D
D
N
G
y
a
l
e
D
p
o
r
P
&
)
e
d
i
s
B
n
o
t
u
p
t
u
o
(
h
g
i
H
e
l
b
a
n
E
/
e
l
b
a
s
i
D
n
e
p
O
Switch Positions
RT
8pF
CL
VCC
VIN
VOUT
500
500
55
5.0V
Pulse
Generator
D.U.T
55
5
PS8571A 12/11/02
PI3B4010
3.3V, High Bandwidth, 40:10-Bit,
DDR Mux/Demux NanoSwitch
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Voltage Waveforms Propagation Delay Times
Switching Waveforms
Output Skew - t
SK(o)
Pulse Skew - t
SK(p)
Input
tPLH
1.25V
1.25V
1.25V
1.25V
tPHL
2.5V
0V
Output
VOH
VOL
Voltage Waveforms Enable and Disable Times
Data In at
Ax or Ay
Data Out
at MBx
Data Out
at MBy
tPLHX
tPHLX
2.5V
1.25V
1.25V
1.25V
I
tSK(o) = I tPLHy tPLHx I or I tPHLy tPHLx I
tSK(o)
tPLHy
tPHLy
VOH
VOL
VOL
VOH
0V
Input
Output
tPLH
tSK(p) = I tPHL tPLH I
tPHL
2.5V
1.25V
1.25V
VOL
VOH
0V
tPLZ
1.25V
1.25V
2.5V
2.5V
0V
0V
0V
1.25V
1.25V
1.25V
1.25V
tPHZ
tPHZ
tPZL
tPZH
tPZH
Output A
Output A
Output B
VOL +0.15V
VOH 0.15V
VOL
VOH
VOH
SEL
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