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Электронный компонент: PI6C104S

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PS8164B 03/15/99
PI6C104
Spread Spectrum Clock Synthesizer
for Desktop Pentium II
PCICLK_F/S1
PCICLK1
VSS
PCICLK3
PCICLK4
PCICLK2
PCICLK5
PCICLK6/PD#
VDD
48M/MODE
24M/REF/S2
VSS
VDD
VDD2
VDD2
CPUCLK0
CPUCLK1
VDD
VSS
SDATA
SCLK
S0
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
XTAL_IN
XTAL_OUT
VDD
APIC
REF1/P14
Pin Configuration
Block Diagram
Features
Up to 112 MHz operation
Spread Spectrum Modulation for CPUCLK, and PCICLK
Two copies of CPU clock with V
DD
of 2.5V 5%
Seven copies of PCI clock,
(synchronous with CPU clock) 3.3V
One copy of Ref. clock @ 14.31818MHz (3.3V
TTL
)
48MHz USB Clock, 24MHz Super I/O clock
I
2
C Serial Configuration Interface
Low cost 14.31818MHz crystal oscillator input
Power management control
Isolated core V
DD
, V
SS
pins for noise reduction
28-pin SSOP (H) and SOIC package (S)
Description
The PI6C104 is a high-speed low-noise clock generator designed
to work with the PI6C18X family of clock buffer to meet all clock
needs for Desktop Intel Architecture platforms. CPU and chipset
clock frequencies from 66.6 MHz to 112 MHz are supported.
Split supplies of 3.3V and 2.5V are used. The 3.3V power supply
powers a portion of the I/O and the core. The 2.5V is used to power
the remaining outputs (CPU and APIC). 2.5V signaling follows
JEDEC standard 8-X. Power sequencing of the 3.3V and 2.5V
supplies is not required.
An asynchronous PD# signal may be used to orderly power down
(or up) the system during power on.
28-Pin
H, S
REF1
APIC
V
DDREF
V
DDAPIC
PCICLK[1:6]
CPUCLK[0:1]
REF
OSC
V
DDCPU
2
6
V
DDPCI
0,1
PCICLK_F
Div
PLL1
SEL
XTAL_OUT
XTAL_IN
S[0..2]
S
DATA
SCLOCK
I
2
C
PLL2
V
DDP
2
PI4
48MHz
24MHz/REF
MUX
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PS8164B 03/15/99
PI6C104
Spread Spectrum Clock Synthesizer
for Desktop Pentium II
Pin Description
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PS8164B 03/15/99
PI6C104
Spread Spectrum Clock Synthesizer
for Desktop Pentium II
PI6C104 I
2
C Address Assignment 0D2H
2-Wire I
2
C Control
The I
2
C interface permits individual enable/disable of each clock
output and test mode enable.
The PI6C104 is a slave receiver device. It can not be read back. Sub
addressing is not supported. All preceding bytes must be sent in
order to change one of the control bytes.
Every byte put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving device.
During normal data transfers SDATA changes only when SCLK is
LOW. Exceptions: A HIGH to LOW transition on SDATA while
SCLK is HIGH indicates a start condition. A LOW to HIGH
transition on SDATA while SCLK is HIGH is a stop condition
and indicates the end of a data transfer cycle.
Each data transfer is initiated with a start condition and ended
with a stop condition. The first byte after a start condition is always
a 7-bit address byte followed by a read/write bit. (HIGH = read
from addressed device, LOW = write to addressed device).
If the devices own address is detected, PI6C104 generates an
acknowledge by pulling SDATA line LOW during ninth clock
pulse, then accepts the following data bytes until another start or
stop condition is detected.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. Command Code byte, and
2. Byte Count byte.
Although the data bits on these two bytes are dont care, they
must be sent and acknowledged.
7
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5
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4
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3
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1
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0
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Clock Enable Configuration
#
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PS8164B 03/15/99
PI6C104
Spread Spectrum Clock Synthesizer
for Desktop Pentium II
Byte 3 : Frequency, Spread Spectrum
Byte 4 : Clock Controls (1 = Enabled, 0 = Disabled)
#
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Byte 5 : PCI Clock Control (1 = Enabled, 0 = Disabled)
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238
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PS8164B 03/15/99
PI6C104
Spread Spectrum Clock Synthesizer
for Desktop Pentium II
Table 1: Byte 3 Frequency and Spread Spectrum Table
Byte 0: Test Mode Table
S
F
S
3
ti
B
N
E
S
S
1
ti
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6
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)
z
H
M
(
I
C
P
)
%
(
d
a
e
r
p
S
1
0
0
0
0
5
7
0
3
F
F
O
1
0
0
0
1
8
.
6
6
4
.
3
3
F
F
O
1
0
0
1
0
6
.
6
6
3
.
3
3
F
F
O
1
0
0
1
1
8
.
6
6
4
.
3
3
F
F
O
1
0
1
0
0
2
1
1
3
.
7
3
F
F
O
1
0
1
0
1
3
.
3
8
3
.
3
3
F
F
O
1
0
1
1
0
0
0
1
3
.
3
3
F
F
O
1
0
1
1
1
0
0
1
3
.
3
3
F
F
O
1
1
0
0
0
5
7
0
3
5
.
0
+
~
5
.
0
-
1
1
0
0
1
8
.
6
6
4
.
3
3
9
.
0
+
~
9
.
0
-
1
1
0
1
0
6
.
6
6
3
.
7
3
0
.
0
+
~
0
.
1
-
1
1
0
1
1
8
.
6
6
4
.
3
3
5
.
0
+
~
5
.
0
-
1
1
1
0
0
2
1
1
3
.
7
3
5
.
0
+
~
5
.
0
-
1
1
1
0
1
3
.
3
8
3
.
3
3
5
.
0
+
~
5
.
0
-
1
1
1
1
0
0
0
1
3
.
3
3
0
.
0
+
~
1
-
1
1
1
1
1
0
0
1
3
.
3
3
0
.
0
+
~
5
.
0
-
1
ti
B
0
ti
B
U
P
C
I
C
P
M
8
4
M
4
2
C
I
P
A
/
F
E
R
e
d
o
M
0
0
1
el
b
a
t
1
el
b
a
t
z
H
M
8
4
f
e
R
/
z
H
M
4
2
z
H
M
8
1
3
.
4
1
l
a
m
r
o
N
0
1
2
/
n
i
X
6
/
n
i
X
2
/
n
i
X
4
/
n
i
X
n
i
X
t
s
e
T
1
0
1
el
b
a
t
1
el
b
a
t
z
H
M
8
4
f
e
R
/
z
H
M
4
2
z
H
M
8
1
3
.
4
1
C
S
S
1
1
Z
-i
H
Z
-i
H
Z
-i
H
Z
-i
H
Z
-i
H
e
t
a
t
s
-i
r
T
Byte 6 : REF Clock Control (1 = Enabled, 0 = Disabled)
#
ti
B
p
u
P
#
n
i
P
e
m
a
N
n
o
it
p
ir
c
s
e
D
7
0
~
D
V
S
R
d
e
v
r
e
s
e
R
6
~
D
V
S
R
d
e
v
r
e
s
e
R
5
4
2
N
E
C
I
P
A
el
b
a
n
E
si
tl
u
af
e
D
,e
l
b
a
n
E
C
I
P
A
4
~
D
V
S
R
d
e
v
r
e
s
e
R
2
1
~
D
V
S
R
d
e
v
r
e
s
e
R
1
6
2
1
N
E
F
R
1
el
b
a
n
E
e
vi
r
d
h
gi
H
1
F
E
R
0
6
2
0
N
E
F
R
0
el
b
a
n
E
e
vi
r
d
h
gi
H
1
F
E
R
0
N
E
F
R
1
N
E
F
R
0
0
e
vi
r
D
w
o
L
1
0
tl
u
af
e
D
,e
vi
r
D
l
a
m
r
o
N
0
1
e
vi
r
D
h
gi
H
1
1
Note: Outputs are disabled @ low state
Notes:
Bit 3 = Enable Software
Frequency Select
Bit 1 = Enable Software
Frequency Select
Bit 6 = Frequency Select 0
Bit 5 = Frequency Select 1
Bit 4 = Frequency Select 0