1
PS8410 08/11/99
REF/SEL2 1
V
DD3.3
2
XTAL_IN 3 3.3V
2.5V
2.5V
3.3V
3.3V
3.3V
XTAL_OUT 4
V
SS3.3
5
V
SS3.3
6
3V66 0 7
3V66 1 8
V
DD3.3
9
V
DD3.3
10
PCI 0 11
PCI 1 12
PCI 2 13
V
SS3.3
14
PCI 3 15
PCI 4 16
V
SS3.3
17
PCI 5 18
PCI 6 19
PCI 7 20
V
DD3.3
21
V
DDA
22
V
SSA
23
V
SS3.3
24
48MHz0 25
48MHz1 26
V
DD3.3
27
SEL0 28
V
SS2.5
APIC0
APIC1
V
DD2.5
CPU 0
V
DD2.5
CPU 1
CPU 2
V
SS2.5
56
V
SS3.3
55
SDRAM0
54
SDRAM1
53
V
DD3.3
52
SDRAM2
51
SDRAM3
50
V
SS3.3
49
SDRAM4
48
SDRAM5
47
V
DD3.3
46
SDRAM6
45
SDRAM7
44
V
SS3.3
43
DCLK
42
V
DD3.3
41
40
39
38
37
36
35
34
33
PWR_DWN#
SCLK
SDATA
SEL1
32
31
30
29
3.3V
56-Pin
(V56)
DCLK
REF
OSC
REF
XIN
XOUT
48 MHz 0-1
3V66 0-1
PCI 0-7
SDRAM 0-7
CPU 0-2
PLL2
PLL1
2
2
APIC 0-1
2
3
8
8
Pin Configuration
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PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
Block Diagram
Features
3 of 2.5V 66/100/133 MHz CPU (CPU[0-2])
2 of 2.5V 33 MHz APIC (APIC[0-1])
9 of 3.3V 100/133 MHz SDRAM (SDRAM[0-7], DCLK)
8 of 3.3V 33 MHz PCI (PCI[0-7])
2 of 3.3V 66 MHz (3V66 [0-1])
2 of 3.3V 48 MHz (48MHz [0-1])
1 of 3.3V 14.3 MHz (REF)
Selectable CPU and SDRAM clocks (on power up only)
Power down function using PWR_DWN#
Spread Spectrum Enable/Disable by I
2
C
I
2
C interface to turn off unused clocks
56 pin SSOP package (V)
Description
Pericom PI6C110E integrates a dual PLL clock generator, SDRAM
buffer and I
2
C interface. The clock generator section comprised
of an oscillator, 2 low jitter phased locked loop, skew control, and
power down logic. The SDRAM buffers are high speed and low
skew to handle data transfers in excess of 133 MHz.
When Spread Spectrum mode is enabled, all clock outputs are
modulated except for REF and 48 MHz[0-1] outputs. These clocks
are down spread linearly (triangular modulation) by +0%, 0.6%.
To minimize power consumption and EMI radiation some unused
outputs can be turned off. Two wire I
2
C interface is used to enable/
disable Spread Spectrum mode, and to turned off PCI clocks, CPU
clocks, and 48 MHz clocks.
For low power sleep mode, the entire device can be placed to power
down mode. Driving the PWR_DWN# to low state disables the
entire chip. In this state the crystal oscillator, and both PLLs are
turned off. Furthermore, all outputs are deactivated to low state, all
inputs are inactive except for PWR_DWN#.
All trademarks are of their respective companies.
V
2
PS8410 08/11/99
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PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
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Pin Description Table
2
L
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1
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1
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3
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3
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1
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1
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0
0
1
=
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3
3
1
=
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C
Frequency Select Function Table
3
PS8410 08/11/99
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PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
Symbol
Parameter
Min.
Max.
Units
Notes
V
IH3
3.3V Input High Voltage
-0.5
4.6
V
1
V
IL3
3.3V Input Low Voltage
-0.5
V
ESD prot.
Input ESD protection
2000
V
2
DC Specifications
DC parameters must be sustainable under steady state (DC) conditions.
Notes:
1. Maximum V
IH
is not to exceed maximum V
DD
.
2. Human body model.
Symbol
Parameter
Min.
Max.
Units
Notes
V
DDA
3.3V Core Supply Voltage
-0.5
4.6
V
V
DD2.5
2.5V I/O Supply Voltage
-0.5
3.6
V
V
DD3.3
3.3V I/O Supply Voltage
-0.5
4.6
V
T
S
Storage Temperature
-65
150
C
Absolute Maximum DC Power Supply
Absolute Maximum DC I/O
Symbol
Parameter
Condition
Min.
Max.
Units Notes
V
DDA
3.3V Core Supply Voltage
3.3V 5%
3.135
3.465
V
2
V
DD3.3
3.3V I/O Supply Voltage
3.3V 5%
3.135
3.465
V
2
V
DD2.5
2.5V I/O Supply Voltage
2.5V 5%
2.375
2.625
V
2
V
IH3
3.3V Input High Voltage
V
DDA
2.0 V
DD
+0.3 V
4
V
IL3
3.3V Input Low Voltage
V
SS
-0.3
0.8
V
4
I
IL
Input Leakage Current 0 <V
IN
<V
DD3.3
-5
+5
A
1,4
C
in
Input Pin Capacitance
5
pF
C
xtal
Xtal Pin Capacitance
13.5
22.5
pF
3
C
out
Output Pin Capacitance
6
pF
L
PIN
Pin Inductance
7
nH
T
A
Ambient Temperature
No Airflow
0
70
C
DC Operating Specification
Notes:
1. Input Leakage Current does not include inputs with Pull-Up or Pull-down resistors.
2. No power sequencing is implied or allowed to be required in the system.
3. As seen by the crystal. Device is intended to be used with a 17-20pF AT crystal.
4. All inputs referenced to 3.3V power supply.
4
PS8410 08/11/99
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PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
Clock Output Buffer DC Characteristics
e
m
a
N
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ff
u
B
V
C
C
)
V
(
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2
6
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2
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-
5
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3
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3
1
.
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0
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-
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2
3
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2
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1
4
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6
V
3
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.
1
7
2
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5
7
3
.
2
7
2
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.
1
0
3
I
X
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L
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T
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=
V
3
.
0
0
3
Type 1: CPU, APIC Clocks
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.
1
9
2
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=
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5
3
1
.
3
3
2
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.
1
9
2
I
X
A
M
L
O
V
T
U
O
=
V
4
.
0
7
2
Type 3: 48 MHz, REF Clocks
l
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2
=
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5
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5
3
1
.
3
=
6
4
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0
.
1
=
4
5
I
X
A
M
L
O
V
T
U
O
V
4
.
0
=
3
5
Type 4: SDRAM Clocks
l
o
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y
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0
.
1
3
3
A
m
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A
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T
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=
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5
3
1
.
3
3
3
I
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V
T
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=
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5
9
.
1
0
3
I
X
A
M
L
O
V
T
U
O
=
V
4
.
0
8
3
Type 5: PCI, 3V66 Clocks
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