1
PS8384D 06/26/01
Product Features
10 MHz to 134 MHz operating range
Zero input-output propagation delay, adjustable by external
capacitive load on FBK input
Multiple configurations, see Available PI6C2308
Configurations table
Input to output delay, less than 200ps
Multiple low skew outputs
- Output-output skew less than 200ps
- Device-device skew less than 600ps
- Two banks of four outputs, Hi-Z by two select inputs
Low Jitter, less than 200ps
3.3V operation
Space-saving Packages:
16-pin, 150-mil SOIC package (W16) (-1, -1H, -2, -3, -4, -6)
16-pin TSSOP package (L16) (-1, -1H)
Available in industrial and commercial temperatures
Functional Description
Providing two banks of four outputs, the PI6C2308 is a 3.3V zero-
delay buffer designed to distribute clock signals in applications
including PC, workstation, datacom, telecom, and high-performance
systems. Each bank of four outputs can be controlled by the select
inputs as shown in the Select Input Decoding Table.
The PI6C2308 provides 8 copies of a clock signal that has 200ps
phase error compared to a reference clock. The skew between the
output clock signals for PI6C2308 is less than 200ps. When there
are no rising edges on the REF input, the PI6C2308 enters a power
down state. In this mode, the PLL is off and all outputs are Hi-Z.
This results in less than 12A of current draw. The Select Input
Decoding Table shows additional examples when the PLL shuts
down. The PI6C2308 configuration table shows all available devices.
The base part, PI6C2308-1, provides output clocks in sync with a
reference clock. With faster rise and fall times, the PI6C2308-1H
is the high drive version of the PI6C2308-1. Depending on which
output drives the feedback pin, PI6C2308-2 provides 2X and 1X
clock signals on each output bank. The PI6C2308-3 allows the user
to obtain 4X and 2X frequencies on the outputs. The PI6C2308-4
provides 2X clock signals on all outputs. PI6C2308 (-1, -2, -3, -4) allows
bank B to be Hi-Z when all output clocks are not required.The
PI6C2308-6 allows bank B to switch from Reference clock to half
of the frequency of Reference clock using the control inputs S1 and
S2 if Bank A is connected to feedback FBK. In addition, using the
control inputs S1 and S2, the PI6C2308-6 allows bank A to switch
from Reference clock to 2X the frequency of Reference clock if
Bank B is connected to feedback FBK. For testing purposes, the
select inputs connect the input clock directly to outputs.
Block Diagrams
Pin Configuration PI6C2308 (1, 1H, 2, 3, 4, 6)
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3.3V Zero-Delay Buffer
PI6C2308
1
2
3
V
DD
4
GND
5
CLKA2
6
CLKB2
7
S1
8
CLKB1
FBK
CLKA3
V
DD
CLKB4
CLKB3
S2
16
15
14
13
12
11
10
9
REF
CLKA1
GND
CLKA4
16-Pin
W, L
PLL
MUX
REF
S2
S1
Select Input
Decoding
FBK
CLKA1
CLKA2
CLKA3
CLKA4
CLKB2
CLKB3
CLKB4
CLKB1
PI6C2308-6
MUX
2
2
PLL
MUX
Extra Divider (-3, -4)
Extra Divider (-2,-3)
REF
S2
S1
Select Input
Decoding
FBK
CLKA1
CLKA2
CLKA3
CLKA4
CLKB2
CLKB3
CLKB4
CLKB1
PI6C2308 (-1, -1H, -2, -3, -4)
2
2
PS8384D 06/26/01
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PI6C2308
3.3V Zero Delay Buffer
2
S
1
S
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4
-
1
[
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Select Input Decoding for PI6C2308 (-1, -1H, -2, -3, -4)
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Available PI6C2308 Configurations
2
S
1
S
]
4
-
1
[
A
K
L
C
]
4
-
1
[
B
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L
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Select Input Decoding for PI6C2308-6
3
PS8384D 06/26/01
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PI6C2308
3.3V Zero Delay Buffer
To close the feedback loop of the PI6C2308, the FBK pin can be
driven from any of the 8 available output pins. The output driving
the FBK pin will be driving a total load of 7pF plus any additional load
that it drives. The relative loading of this output (with respect to the
remaining outputs) can adjust the input-output delay. This is shown
in the graph above.
Zero Delay and Skew Control
REF. Input to CLKA/CLKB Delay vs. Difference in Loading between FBK pin and CLKA/CLKB pins
Maximum Ratings
Supply Voltage to Ground Potential ...................0.5V to +7.0V
DC Input Voltage (Except REF) ..................0.5V to V
DD
+0.5V
DC Input Voltage REF................................................ 0.5 to 7V
Storage Temperature ........................................ 65C to +150C
Maximum Soldering Temperature (10 seconds)................ 260C
Junction Temperature ....................................................... 150C
Static Discharge Voltage
(per MIL-STD-883, Method 3015).................................. >2000V
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Operating Conditions
(Over operating range, T
A
= 0C to +70C, V
CC
= 3.3V 0.3V)
For applications requiring zero input-output delay, all outputs
including the one providing feedback should be equally loaded. If
input-output delay adjustments are required, use the above graph to
calculate loading differences between the feedback output and
remaining outputs.
600
800
400
200
0
-200
-400
-600
-800
-900
-1000
-25
-20
-15
-10
-5
0
5
10
15
20
25
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
REF
-
Input
to
CLKA/CLKB
Delay
(ps)
PI6C2308-1H
PI6C2308-1,2,3,4,6
4
PS8384D 06/26/01
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PI6C2308
3.3V Zero Delay Buffer
Electrical Characteristics for Commercial Temperature Devices
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Pin Description
5
PS8384D 06/26/01
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PI6C2308
3.3V Zero Delay Buffer
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. REF and FBK inputs have a threshhold voltage of V
DD
/2.
5. For definition of t
1-8
, see Switching Waveforms on page 8.
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Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. REF and FBK inputs have a threshhold voltage of V
DD
/2.
5. For definition of t
1-8
, see Switching Waveforms on page 8.
8
PS8384D 06/26/01
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PI6C2308
3.3V Zero Delay Buffer
V
DD
C
LOAD
V
DD
GND
GND
CLK out
OUTPUTS
0.1
m
F
0.1
m
F
Test Circuit for all parameters except t
8
V
DD
10pF
V
DD
GND
GND
CLK out
OUTPUTS
0.1
m
F
0.1
m
F
Test Circuit for t
8
,Output slew rate on -1H device
1k
W
1k
W
Switching Waveforms
Test Circuit #2
Test Circuit #1
t
2
t
1
1.4V
1.4V
1.4V
t
4
t
3
0.8V
2.0V
0.8V
2.0V
OUTPUT
0V
3.3V
1.4V
t
5
OUTPUT
1.4V
OUTPUT
V
DD
/2
t
6
INPUT
V
DD
/2
FBK
V
DD
/2
t
7
FBK Device 1
V
DD
/2
FBK Device 2
Duty Cycle Timing
All Outputs Rise/Fall Time
Output-Output Skew
Input-Output Propagation Delay
Device-Device Skew
9
PS8384D 06/26/01
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PI6C2308
3.3V Zero Delay Buffer
16-Pin SOIC (W)
Note: Controlling dimensions in millimeters. Ref: JEDEC MS - 012 AC
16-Pin TSSOP (L)
SEATING PLANE
.050
BSC
1
16
0-8
.149
.157
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
3.78
3.99
.386
.393
9.80
10.00
1.27
.053
.068
1.35
1.75
.2284
.2440
5.80
6.20
.0040
.0098
0.10
0.25
.013
.020
.0155
.0260
0.330
0.508
0.393
0.660
.0075
.0098
0.25
0.50
.0099
.0196
x 45
0.19
0.25
.016
.050
0.41
1.27
REF
.193
.201
.047
max.
.002
.006
SEATING
PLANE
.0256
BSC
.018
.030
.004
.008
.252
BSC
1
16
.169
.177
X.XX
X.XX
DENOTES CONTROLLING
DIMENSIONS IN MILLIMETERS
0.05
0.15
6.4
0.45
0.75
0.09
0.20
4.3
4.5
1.20
4.9
5.1
0.65
0.19
0.30
.007
.012
10
PS8384D 06/26/01
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PI6C2308
3.3V Zero Delay Buffer
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
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Ordering Information (Commercial Temperature Device)
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Ordering Information (Industrial Temperature Device)
PDF 
ZIP