1
PS8435B 07/25/00
Product Pin Configuration
Product Description
The PI6C2520 is a low-skew, low-jitter, phase-locked loop (PLL)
clock driver, distributing low-noise clock signals for Networking
Applications. By connecting the feedback FB_OUT output to the
feedback FB_IN input, the propagation delay from the CLK_IN
input to any clock output will be nearly zero. This zero-delay
feature allows the CLK_IN input clock to be distributed, providing
5 banks of 4 clocks and an extra clock for feedback.
For test purposes, the PLL can be bypassed by strapping AV
CC
to
ground. The PI6C2520, which allows a Spread Spectrum clock in-
put, operates at 3.3V V
CC
and provides integrated series-damping
resistors that make it ideal for driving point-to-point loads. Output
signal duty cycles are adjusted to 50 percent, independent of the
duty cycle at the input clock.
Each bank of outputs can be enabled or disabled via the 1G, 2G,
3G, 4G, and 5G control inputs. When the G inputs are high, the
outputs switch in phase and frequency with CLK_IN. When the G
inputs are low, the outputs are disabled to the logic low state.
Product Features
Low-Noise Phase-Locked Loop Clock Distribution.
Allows Clock Input to have Spread Spectrum modulation
for EMI reduction. The clock outputs track the Clock Input
modulation.
Maximum clock frequency of 125 MHz.
Zero Input-to-Output delay.
Low jitter: Cycle-to-Cycle jitter 100ps max.
On-chip series damping resistor at clock output drivers for
low noise and EMI reduction.
Operates at 3.3V V
CC
.
Output-to-Output skew less than 200ps.
Package: Plastic 56-pin TSSOP (A).
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PI6C2520
Low-Noise Phase-Locked Loop
Clock Driver with 20 Clock Outputs
Block Diagram
CLK_IN
FB_IN
AVCC
4
5Y [0:3]
FB_OUT
5G
PLL
4
3Y [0:3]
3G
4
4Y [0:3]
4G
4
2Y [0:3]
2G
4
1Y [0:3]
1G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VCC
1Y0
1Y1
GND
GND
1Y2
1Y3
VCC
1G
GND
AVCC
CLK_IN
AGND
5G
GND
2G
VCC
2Y0
2Y1
GND
GND
2Y2
2Y3
VCC
VCC
5Y0
5Y1
GND
VCC
4Y0
4Y1
GND
GND
4Y2
4Y3
VCC
4G
GND
AVCC
FB_IN
AGND
FB_OUT
GND
3G
VCC
3Y0
3Y1
GND
GND
3Y2
3Y3
VCC
VCC
5Y3
5Y2
GND
56-Pin
A
PI6C2520
Low-Noise, Phase-Locked Loop
Clock Driver with 20 Clock Outputs
2
PS8435B 07/25/00
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Pin Functions
PI6C2520
Low-Noise, Phase-Locked Loop
Clock Driver with 20 Clock Outputs
3
PS8435B 07/25/00
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Supply voltage range, V
CC ...................................................................................................................................................
0.5V to 4.6V
Input voltage range, V
I
(1) ....................................................................................................................................................
0.5V to 6.5V
Voltage range applied to any output in the high or low state, V
O(1,2) ...................................................
0.5V to V
CC
+0.5V
Input clamp current, I
IK
(V
I
<0) ......................................................................................................................... 50mA
Output clamp current, I
OK
(V
O
<0 or V
O
> V
CC
) ............................................................................................... 50mA
Continuous output current, I
O
(V
O
- 0 to V
CC
) ................................................................................................. 50mA
Continuous current through each V
CC
or GND .............................................................................................. 100mA
Maximum power dissipation at T
A
= 55C (in still air)
(3) ........................................................................................................
0.85W
Storage Temperature Range, T
stg ...................................................................................................................................
65C to 150C
Absolute Maximum Ratings
(Over Operating Free-Air Temperature, unless otherwise noted)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure
to Absolute-Maximum-Rated conditions for extended periods may affect device reliability.
Notes:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6V maximum.
3. Maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
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C
Recommended Operating Conditions
(4)
Notes:
4. Unused inputs must be held high or low to prevent them from floating.
Function Table
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Note:
x is from 1 to 5
PI6C2520
Low-Noise, Phase-Locked Loop
Clock Driver with 20 Clock Outputs
4
PS8435B 07/25/00
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Electrical Characteristics
(Over Recommended Operating Free-air Temperature Range, unless otherwise noted)
Notes:
1. For Min. or Max. conditions, use the appropriate value specified under recommended operating conditions.
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Switching Characteristics
(Over Recommended Ranges of Supply Voltage & Operating Free-Air Temperature, C
L
= 22pF)
(1,3)
Notes:
1. These parameters are not production tested.
2. The t
sk(o)
specification is only valid for equal loading of all outputs.
3. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
Timing Requirements
(Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature).
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PI6C2520
Low-Noise, Phase-Locked Loop
Clock Driver with 20 Clock Outputs
5
PS8435B 07/25/00
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Parameter Measurement Information
Load Circuit
From Output
Under Test
22pF
500
50% V
CC
50% V
CC
3V
0V
50% V
CC
V
OH
V
OL
Input
Output
t
pd
t
r
t
f
80%
20%
80%
20%
Voltage Waveforms
Propagation Delay times
Notes:
1. C
L
includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: CLK_IN
100MHz, Z
O
= 50 ohms, t
r
1.2ns, t
f
1.2ns.
3. The outputs are measured one at a time with one transition per measurement.
CLK_IN
FB_IN
FB_OUT
Any Y
t
phase
error
t
sk(O)
Any Y
Any Y
t
sk(O)
Phase Error and Skew Calculations
PI6C2520
Low-Noise, Phase-Locked Loop
Clock Driver with 20 Clock Outputs
6
PS8435B 07/25/00
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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
56-pin Thin Shrink Small-Outline Package (A)
.002
.006
SEATING PLANE
.007
.011
.004
.008
1
56
.236
.244
0.50
0.17
0.27
0.05
0.15
0.09
0.20
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
.018
.030
0.45
0.75
.047
Max.
1.20
6.0
6.2
.547
.555
13.9
14.1
.319
8.1
.0197
BSC
BSC
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6
5
Ordering Information
PDF 
ZIP