PI74FCT16373/162373/162H373T
16-BIT TRANSPARENT LATCHES
1
PS2033A 03/11/96
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Logic Block Diagram
Product Features:
Common Features:
PI74FCT16373T, PI74FCT162373T, and PI74FCT162H373T are
high-speed,
low power devices with high current drive.
Vcc = 5V 10%
Hysteresis on all inputs
Packages available:
48-pin 240 mil wide plastic TSSOP (A)
48-pin 300 mil wide plastic SSOP (V)
PI74FCT16373T Features:
High output drive: I
OH
= 32 mA; I
OL
= 64 mA
Power off disable outputs permit "live insertion"
Typical V
OLP
(Output Ground Bounce) < 1.0V
at V
CC
= 5V, T
A
= 25C
PI74FCT162373T Features:
Balanced output drivers: 24 mA
Reduced system switching noise
Typical V
OLP
(Output Ground Bounce) < 0.6V
at V
CC
= 5V, T
A
= 25C
PI74FCT162H373T Features:
Bus Hold retains last active bus state during 3-state
Eliminates the need for external pull-up resistors
Product Description:
Pericom Semiconductor's PI74FCT series of logic circuits are pro-
duced in the Company's advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
The PI74FCT16373T, PI74FCT162373T, and PI74FCT162H373T
are 16-bit transparent latches designed with 3-state outputs and are
intended for bus oriented applications. The Output Enable and
Latch Enable controls are organized to operate as two 8-bit latches
or one 16-bit latch. When Latch Enable (LE) is HIGH, the flip-flops
appear transparent to the data. The data that meets the set-up time
when LE is LOW is latched. When OE is HIGH, the bus output is
in the high impedance state.
The PI74FCT16373T output buffers are designed with a Power-
Off disable allowing "live insertion" of boards when used as
backplane drivers.
The PI74FCT162373T has 24 mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
The PI74FCT162H373T has "Bus Hold" which retains the input's
last state whenever the input goes to high-impedance preventing
"floating" inputs and eliminating the need for pull-up/down resistors.
PI74FCT16373T
PI74FCT162373T
PI74FCT162H373T
Fast CMOS 16-Bit
Transparent Latches
1
OE
1
LE
1
O
0
C
D
1
D
0
TO 7 OTHER CHANNELS
2
OE
2
LE
2
O
0
C
D
2
D
0
TO 7 OTHER CHANNELS
PI74FCT16373/162373/162H373T
16-BIT TRANSPARENT LATCHES
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Product Pin Description
Pin Name
Description
xOE
Output Enable Inputs (Active LOW)
xLE
Latch Enable Inputs (Active HIGH)
xDx
Inputs
(1)
xOx
3-State Outputs
GND
Ground
V
CC
Power
Inputs
(1)
Outputs
(1)
X
D
X
X
OE
xLE
xOx
H
L
H
H
L
L
H
L
X
H
X
Z
Truth Table
Note:
1. H = High Voltage Level, X = Don't Care, L = Low
Voltage Level, Z = High Impedance
Product Pin Configuration
Note:
1. For the PI74FCT162H373T, these pins have "Bus
Hold." All other pins are standard, outputs, or I/Os.
1
2
3
4
5
6
7
8
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
32
31
30
29
28
27
26
25
1
OE
1
O
0
1
O
1
GND
1
O
2
1
O
3
V
CC
1
O
4
1
O
5
GND
1
O
6
1
O
7
2
O
0
2
O
1
GND
2
O
2
2
O
3
V
CC
2
O
4
2
O
5
GND
2
O
6
2
O
7
2
OE
1
LE
1
D
0
1
D
1
GND
1
D
2
1
D
3
V
CC
1
D
4
1
D
5
GND
1
D
6
1
D
7
2
D
0
2
D
1
GND
2
D
2
2
D
3
V
CC
2
D
4
2
D
5
GND
2
D
6
2
D
7
2
LE
48-PIN
V48
A48
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DC Electrical Characteristics
(Over the Operating Range, T
A
= 40C to +85C, V
CC
= 5.0V 10%)
Parameters
Description
Test Conditions
(1)
Min.
Typ
(2)
Max.
Units
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH Level
2.0
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW Level
0.8
V
I
IH
Input HIGH Current
Standard Input
, V
CC
= Max.
V
IN
= V
CC
1
A
I
IH
Input HIGH Current
Standard I/O, V
CC
= Max.
V
IN
= V
CC
1
A
I
IH
Input HIGH Current
Bus Hold Input
(4)
, V
CC
= Max.
V
IN
= V
CC
100
A
I
IH
Input HIGH Current
Bus Hold I/O
(4)
, V
CC
= Max.
V
IN
= V
CC
100
A
I
IL
Input LOW Current
Standard Input
, V
CC
= Min.
V
IN
= GND
1
A
I
IL
Input LOW Current
Standard I/O, V
CC
= Min.
V
IN
= GND
1
A
I
IL
Input LOW Current
Bus Hold Input
(4)
, V
CC
= Min.
V
IN
= GND
100
A
I
IL
Input LOW Current
Bus Hold I/O
(4)
, V
CC
= Min.
V
IN
= GND
100
A
I
BHH
Bus Hold
Bus Hold Input
(4)
, V
CC
= Min.
V
IN
= 2.0V
50
A
I
BHL
Sustain Current
V
IN
= 0.8V
+50
I
OZH
(5)
High Impedance
V
CC
= Max.
V
OUT
= 2.7V
1
A
I
OZL
(5)
Output Current
V
CC
= Max.
V
OUT
= 0.5V
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18 mA
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max.
(3)
, V
OUT
= GND
80
140
200
mA
I
O
Output Drive Current
V
CC
= Max.
(3)
, V
OUT
= 2.5V
50
180
mA
V
H
Input Hysteresis
100
mV
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................................................... 65C to +150C
Ambient Temperature with Power Applied .................................... 40C to +85C
Supply Voltage to Ground Potential (Inputs & Vcc Only) .............. 0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) ........... 0.5V to +7.0V
DC Input Voltage ............................................................................ 0.5V to +7.0V
DC Output Current ..................................................................................... 120 mA
Power Dissipation .......................................................................................... 1.0W
Note:
Stresses greater than those listed under
MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect reliability.
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Pins with Bus Hold are identified in the pin description.
5. This specification does not apply to bi-directional functionalities with Bus Hold.
PI74FCT16373/162373/162H373T
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PI74FCT16373T Output Drive Characteristics
(Over the Operating Range)
Parameters Description
Test Conditions
(1)
Min.
Typ
(2)
Max.
Units
V
OH
Output HIGH Voltage
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OH
= 3.0 mA
2.5
3.5
V
I
OH
= 15.0 mA
2.4
3.5
I
OH
= 32.0 mA
2.0
3.0
V
OL
Output LOW Voltage
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OL
= 64 mA
0.2
0.55
V
I
OFF
Power Down Disable
V
CC
= 0V, V
IN
or V
OUT
4.5V
--
--
100
A
PI74FCT162373T/162H373T Output Drive Characteristics
(Over the Operating Range)
Parameters
Description
Test Conditions
(1)
Min.
Typ
(2)
Max.
Units
V
OH
Output HIGH Voltage
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OH
= 24.0 mA
2.4
3.3
V
V
OL
Output LOW Voltage
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OL
= 24 mA
0.3
0.55
V
I
ODL
Output LOW Current
V
CC
= 5V, V
IN
= V
IH
OR
V
IL
, V
OUT
= 1.5V
(3)
60
115
150
mA
I
ODH
Output HIGH Current
V
CC
= 5V, V
IN
= V
IH
OR
V
IL
, V
OUT
= 1.5V
(3)
60
115
150
mA
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is determined by device characterization but is not production tested.
Capacitance
(T
A
= 25C, f = 1 MHz)
Parameters
(4)
Description
Test Conditions
Typ
Max.
Units
C
IN
Input Capacitance
V
IN
= 0V
4.5
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
5.5
8
pF
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16-BIT TRANSPARENT LATCHES
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Power Supply Characteristics
Parameters Description
Test Conditions
(1)
Min.
Typ
(2)
Max.
Units
I
CC
Quiescent Power
V
CC
= Max.
V
IN
= GND or V
CC
0.1
500
A
Supply Current
I
CC
Supply Current per
V
CC
= Max.
V
IN
= 3.4V
(3)
0.5
1.5
mA
Input @ TTL HIGH
I
CCD
Supply Current per
V
CC
= Max.,
V
IN
= V
CC
60
100
A/
Input per MHz
(4)
Outputs Open
V
IN
= GND
MHz
X
OE = GND,
X
LE = V
CC
One Bit Toggling
50% Duty Cycle
I
C
Total Power Supply
V
CC
= Max.,
V
IN
= V
CC
0.6
1.5
(5)
mA
Current
(6)
Outputs Open
V
IN
= GND
f
I
= 10 MH
Z
50% Duty Cycle
X
OE = GND,
X
LE = V
CC
One Bit Toggling
V
IN
= 3.4V
0.9
2.3
(5)
V
IN
= GND
V
CC
= Max.,
V
IN
= V
CC
2.4
4.5
(5)
Outputs Open
V
IN
= GND
f
I
= 2.5 MH
Z
50% Duty Cycle
X
OE = GND,
X
LE = V
CC
16 Bits Toggling
V
IN
= 3.4V
6.4
16.5
(5)
V
IN
= GND
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 5.0V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. I
C
=I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
I
N
I
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
I
= Input Frequency
N
I
= Number of Inputs at f
I
All currents are in milliamps and all frequencies are in megahertz.
PI74FCT16373/162373/162H373T
16-BIT TRANSPARENT LATCHES
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PI74FCT16373T Switching Characteristics over Operating Range
16373T
16373AT
16373CT
16373DT
16373ET
C o m .
C o m .
C o m .
C o m .
C o m .
Parameters
Description
Conditions
(1)
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
t
PLH
Propagation Delay
C
L
= 50 pF
1.5
8.0
1.5
5.2
1.5
4.2
1.5
3.8
1.5
3.4
ns
t
PHL
xDx to xOx
R
L
= 500
t
PLH
Propagation Delay
2.0
13.0
2.0
8.5
2.0
5.5
1.5
4.0
1.5
3.7
ns
t
PHL
xLE to xOx
t
PZH
Output Enable Time
1.5
12.0
1.5
6.5
1.5
5.5
1.5
4.8
1.5
4.4
ns
t
PZL
xOE to xOx
t
PHZ
Output Disable Time
(3)
1.5
7.5
1.5
5.5
1.5
5.0
1.5
4.0
1.5
4.0
ns
t
PLZ
xOE to xOx
t
SU
Setup Time HIGH
2.0
--
2.0
--
2.0
--
1.5
--
1.0
--
ns
or LOW,
X
D
X
to
X
LE
t
H
Hold Time HIGH
1.5
--
1.5
--
1.5
--
1.0
--
1.0
--
ns
or LOW,
X
D
X
to
X
LE
t
W
xLE Pulse Width
6.0
--
5.0
--
5.0
--
3.0
--
3.0
--
ns
HIGH
(3)
t
SK
(o)
Output Skew
(4)
--
0.5
--
0.5
--
0.5
--
0.5
--
0.5
ns
PI74FCT162373T Switching Characteristics over Operating Range
162373T
162373AT
162373CT
162373DT
162373ET
C o m .
C o m .
C o m .
C o m .
C o m .
Parameters
Description
Conditions
(1)
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
t
PLH
Propagation Delay
C
L
= 50 pF
1.5
8.0
1.5
5.2
1.5
4.2
1.5
3.8
1.5
3.4
ns
t
PHL
xDx to xOx
R
L
= 500
t
PLH
Propagation Delay
2.0
13.0
2.0
8.5
2.0
5.5
1.5
4.0
1.5
3.7
ns
t
PHL
xLE to xOx
t
PZH
Output Enable Time
1.5
12.0
1.5
6.5
1.5
5.5
1.5
4.8
1.5
4.4
ns
t
PZL
xOE to xOx
t
PHZ
Output Disable Time
(3)
1.5
7.5
1.5
5.5
1.5
5.0
1.5
4.0
1.5
4.0
ns
t
PLZ
xOE to xOx
t
SU
Setup Time HIGH
2.0
--
2.0
--
2.0
--
1.5
--
1.0
--
ns
or LOW,
X
D
X
to
X
LE
t
H
Hold Time HIGH
1.5
--
1.5
--
1.5
--
1.0
--
1.0
--
ns
or LOW,
X
D
X
to
X
LE
t
W
xLE Pulse Width
6.0
--
5.0
--
5.0
--
3.0
--
3.0
--
ns
HIGH
(3)
t
SK
(o)
Output Skew
(4)
--
0.5
--
0.5
--
0.5
--
0.5
--
0.5
ns
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
PI74FCT16373/162373/162H373T
16-BIT TRANSPARENT LATCHES
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PI74FCT162H373T Switching Characteristics over Operating Range
162H373T
162H373AT 162H373CT 162H373DT 162H373ET
Com.
Com.
Com.
Com.
Com.
Parameters
Description
Conditions
(1)
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
t
PLH
Propagation Delay
C
L
= 50 pF
1.5
8.0
1.5
5.2
1.5
4.2
1.5
3.8
1.5
3.4
ns
t
PHL
xDx to xOx
R
L
= 500
t
PLH
Propagation Delay
2.0
13.0
2.0
8.5
2.0
5.5
1.5
4.0
1.5
3.7
ns
t
PHL
xLE to xOx
t
PZH
Output Enable Time
1.5
12.0
1.5
6.5
1.5
5.5
1.5
4.8
1.5
4.4
ns
t
PZL
xOE to xOx
t
PHZ
Output Disable Time
(3)
1.5
7.5
1.5
5.5
1.5
5.0
1.5
4.0
1.5
4.0
ns
t
PLZ
xOE to xOx
t
SU
Setup Time HIGH
2.0
--
2.0
--
2.0
--
1.5
--
1.0
--
ns
or LOW,
X
D
X
to
X
LE
t
H
Hold Time HIGH
1.5
--
1.5
--
1.5
--
1.0
--
1.0
--
ns
or LOW,
X
D
X
to
X
LE
t
W
xLE Pulse Width
6.0
--
5.0
--
5.0
--
3.0
--
3.0
--
ns
HIGH
(3)
t
SK
(o)
Output Skew
(4)
--
0.5
--
0.5
--
0.5
--
0.5
--
0.5
ns
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
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