1
PS2039B 02/24/99
Logic Block Diagram
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PI74FCT16646T
PI74FCT162646T
PI74FCT162H646T
Product Description
Pericom Semiconductors PI74FCT series of logic circuits are
pro duced in the Companys advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
The PI74FCT16646T, PI74FCT162646T, and PI74FCT162H646
are 16-bit registered transceivers organized as two independent
8-bit bus transceivers designed with 3-state D-type flip-flops and
control circuitry arranged for multiplexed transmission of data
directly from the data bus or from the internal storage registers. Each
8-bit transceiver utilizes the enable control (xOE) and direction pins
(xDIR) to control the transceiver functions. The Select (xSAB and
xSBA) control pins are used to select either real-time or stored data
transfer. The circuitry used for select control will eliminate the
typical decoding glitch that occurs in a multiplexer during the
transition between real-time and stored data. A low input level
selects real-time data and a high selects stored data.
The PI74FCT16646T output buffers are designed with a Power-Off
disable allowing live insertion of boards when used as backplane
drivers.
The PI74FCT162646T has 24mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
The PI74FCT162H646T has Bus Hold which retains the inputs
last state whenever the input goes to high-impedance preventing
floating inputs and eliminating the need for pull-up/down resistors.
Product Features
Common Features:
PI74FCT16646T, PI74FCT162646T, and PI74FCT162H646 are
high-speed, low power devices with high current drive
V
CC
= 5V 10%
Hysteresis on all inputs
Packages available:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 173 mil wide plastic TVSOP (JEDEC TSSOP K)
56-pin 300 mil wide plastic SSOP (V)
PI74FCT16646T Features:
High output drive: I
OH
= 32mA; I
OL
= 64mA
Power off disable outputs permit live insertion
Typical V
OLP
(Output Ground Bounce)
< 1.0V at V
CC
= 5V, T
A
= 25C
PI74FCT162646T Features:
Balanced output drivers: 24mA
Reduced system switching noise
Typical V
OLP
(Output Ground Bounce)
< 0.6V at V
CC
= 5V, T
A
= 25C
PI74FCT162H646T Features:
Bus Hold retains last active bus state during Three-state
Eliminates the need for external pull-up resistors
1
Fast CMOS 16-Bit
Registered Transceivers
D
1
CLKAB
C
1
CLKBA
1
SBA
1
DIR
1
OE
1
SAB
D
C
A REG
B REG
1
B0
1
A0
TO 7 OTHER CHANNELS
D
2
CLKAB
C
2
CLKBA
2
SBA
2
DIR
2
OE
2
SAB
D
C
A REG
B REG
2
B0
2
A0
TO 7 OTHER CHANNELS
PI74FCT16646T/162646T/162H646T
16-Bit Registered Transceivers
2
PS2039B 02/24/99
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
25
26
27
28
32
31
30
29
1
DIR
1
CLKAB
1
SAB
GND
1
A
0
1
A
1
VCC
1
A
2
1
A
3
1
A
4
GND
1
A
5
1
A
6
1
A
7
2
A
0
2
A
1
2
A
2
GND
2
A
3
2
A
4
2
A
5
V
CC
2
A
6
2
A
7
GND
2
SAB
2
CLKAB
2
DIR
1
OE
1
CLKBA
1
SBA
GND
1
B
0
1
B
1
VCC
1
B
2
1
B
3
1
B
4
GND
1
B
5
1
B
6
1
B
7
2
B
0
2
B
1
2
B
2
GND
2
B
3
2
B
4
2
B
5
V
CC
2
B
6
2
B
7
GND
2
SBA
2
CLKBA
2
OE
Product Pin Configuration
Notes:
1.The data output functions may be enabled or disabled by various signals at the xOE or xDIR inputs.
Data input functions are always enabled, i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.
2. Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered to load both registers.
H = High Voltage Level; L = Low Voltage Level; X = Don't Care;
= LOW-to-HIGH transition
Pin Name
Description
xAx
(1)
Data Register A Inputs
Data Register B Outputs
xBx
(1)
Data Register B Inputs
Data Register A Outputs
xCLKAB, xCLKBA
Clock Pulse Inputs
SAB, SBA
Output Data Source Select Inputs
xDIR, xOE
Output Enable Inputs
GND
Ground
V
CC
Power
Note: 1.For the PI74FCT162H646T, these pins have
"Bus Hold." All other pins are standard, outputs, or I/Os.
Product Pin Description
Inputs
DATA I/O
(2)
Function/Operation
xOE
X
DIR
X
CLKAB
X
CLKBA
X
SAB
X
SBA
X
A
X
X
B
X
Isolation
H
X
H or L
H or L
X
X
Input
Input
Store A and B Data
H
X
X
X
Real Time B Data to A Bus
L
L
X
X
X
L
Output
Input
Stored B Data to A Bus
L
L
X
H or L
X
H
Real Time A Data to B Bus
L
H
X
X
L
X
Input
Output
Stored A Data to B Bus
L
H
H or L
X
H
X
Truth Table
56-PIN
V56
A56
K56
PI74FCT16646T/162646T/162H646T
16-Bit Registered Transceivers
3
PS2039B 02/24/99
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REAL-TIME TRANSFER
BUS B TO A
REAL-TIME TRANSFER
BUS A TO B
STORAGE FROM
A AND/OR B
TRANSFER STORES
DATA TO A AND/OR B
xDIR xOE
xCLKAB
xCLKBA
xSAB
xSBA
H
L
X
X
X
L
L
X
X
X
X
H
X
X
xDIR xOE
xCLKAB
xCLKBA
xSAB
xSBA
L
L
X
H or L
X
H
H
L
H or L
X
H
X
BUS
A
BUS
B
BUS
A
BUS
B
xDIR xOE
xCLKAB
xCLKBA
xSAB
xSBA
L
L
X
X
X
L
xDIR xOE
xCLKAB
xCLKBA
xSAB
xSBA
H
L
X
X
L
X
BUS
A
BUS
B
BUS
A
BUS
B
PI74FCT16646T/162646T/162H646T
16-Bit Registered Transceivers
4
PS2039B 02/24/99
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DC Electrical Characteristics
(Over the Operating Range, T
A
= 40C to +85C, V
CC
= 5.0V 10%)
Parameters Description
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Units
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH Level
2.0
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW Level
0.8
V
I
IH
Input HIGH Current
Standard Input, V
CC
= Max.
V
IN
= V
CC
1
A
I
IH
Input HIGH Current
Standard I/O, V
CC
= Max.
V
IN
= V
CC
1
A
I
IH
Input HIGH Current
Bus Hold Input
(4)
, V
CC
= Max.
V
IN
= V
CC
100
A
I
IH
Input HIGH Current
Bus Hold I/O
(4)
, V
CC
= Max.
V
IN
= V
CC
100
A
I
IL
Input LOW Current
Standard Input, V
CC
= Min.
V
IN
= GND
1
A
I
IL
Input LOW Current
Standard I/O, V
CC
= Min.
V
IN
= GND
1
A
I
IL
Input LOW Current
Bus Hold Input
(4)
, V
CC
= Min.
V
IN
= GND
100
A
I
IL
Input LOW Current
Bus Hold I/O
(4)
, V
CC
= Min.
V
IN
= GND
100
A
I
BHH
Bus Hold
Bus Hold Input
(4)
, V
CC
= Min.
V
IN
= 2.0V
50
A
I
BHL
Sustain Current
V
IN
= 0.8V
+50
I
OZH(5)
High-Impedance
V
CC
= Max.
V
OUT
= 2.7V
1
A
I
OZL(5)
Output Current
V
CC
= Max.
V
OUT
= 0.5V
1
A
(3-S
TATE
O
UTPUTS
)
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max.
(3)
, V
OUT
= GND
80
140
200
mA
I
O
Output Drive Current
V
CC
= Max.
(3)
, V
OUT
= 2.5V
50
180
mA
V
H
Input Hysteresis
100
mV
Storage Temperature ................................................................. 65C to +150C
Ambient Temperature with Power Applied ................................ 40C to +85C
Supply Voltage to Ground Potential (Inputs & Vcc Only) .......... 0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) ....... 0.5V to +7.0V
DC Input Voltage ......................................................................... 0.5V to +7.0V
DC Output Current .................................................................................... 120mA
Power Dissipation ......................................................................................... 1.0W
Note:
Stresses greater than those listed under
MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these
or any other conditions above those indicated in
the operational sections of this specification is
not implied. Exposure to absolute maximum
rating conditions for extended periods may
affect reliability.
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Pins with Bus Hold are identified in the pin description.
5. This specification does not apply to bi-directional functionalities with Bus Hold.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
PI74FCT16646T/162646T/162H646T
16-Bit Registered Transceivers
5
PS2039B 02/24/99
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PI74FCT16646T Output Drive Characteristics
(Over the Operating Range)
Parameters Description
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Units
V
OH
Output HIGH Voltage
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OH
= 3.0mA
2.5
3.5
V
I
OH
= 15.0mA
2.4
3.5
I
OH
= 32.0mA
2.0
3.0
V
OL
Output LOW Voltage
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OL
= 64mA
0.2
0.55
V
I
OFF
Power Down Disable
V
CC
= 0V, V
IN
or V
OUT
4.5V
--
--
100
A
PI74FCT162646T/162H646T Output Drive Characteristics
(Over the Operating Range)
Parameters Description
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Units
V
OH
Output HIGH Voltage
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OH
= 24.0mA
2.4
3.3
V
V
OL
Output LOW Voltage
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OL
= 24mA
0.3
0.55
V
I
ODL
Output LOW Current
V
CC
= 5V, V
IN
= V
IH
OR
V
IL
, V
OUT
= 1.5V
(3)
60
115
150
mA
I
ODH
Output HIGH Current
V
CC
= 5V, V
IN
= V
IH
OR
V
IL
, V
OUT
= 1.5V
(3)
60
115
150
mA
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is determined by device characterization but is not production tested.
Capacitance
(T
A
= 25C, f = 1 MHz)
Parameters
(4)
Description
Test Conditions
Typ.
Max.
Units
C
IN
Input Capacitance
V
IN
= 0V
4.5
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
5.5
8
pF
PI74FCT16646T/162646T/162H646T
16-Bit Registered Transceivers
6
PS2039B 02/24/99
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Power Supply Characteristics
Parameters Description
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Units
I
CC
Quiescent Power
V
CC
= Max.
V
IN
= GND or V
CC
0.12
500
A
Supply Current
I
CC
Supply Current per
V
CC
= Max.
V
IN
= 3.4V
(3)
0.5
1.5
mA
Input @ TTL HIGH
I
CCD
Supply Current per
V
CC
= Max., Outputs Open V
IN
= V
CC
75
120
A/
Input per MHz
(4)
xDIR = xOE = GND
V
IN
= GND
MHz
One Bit Toggling
50% Duty Cycle
I
C
Total Power Supply
V
CC
= Max.,
V
IN
= V
CC
0.8
1.7
(5)
mA
Current
(6)
Outputs Open
V
IN
= GND
f
CP
= 10 MH
Z
(
X
CLKBA)
50% Duty Cycle
xDIR = xOE = GND
One Bit Toggling
V
IN
= 3.4V
1.3
3.2
(5)
f
I
= 5 MH
Z
V
IN
= GND
50% Duty Cycle
V
CC
= Max.,
V
IN
= V
CC
3.8
6.5
(5)
Outputs Open
V
IN
= GND
f
CP
= 10 MH
Z
(
X
CLKBA)
50% Duty Cycle
xDIR = xOE = GND
16 Bits Toggling
V
IN
= 3.4
8.3
20.0
(5)
f
I
= 2.5 MH
Z
V
IN
= GND
50% Duty Cycle
Notes:
1. For Max. or Min. conditions use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 5.0V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. I
C
=I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
I
N
I
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
I
= Input Frequency
N
I
= Number of Inputs at f
I
All currents are in milliamps and all frequencies are in megahertz.
PI74FCT16646T/162646T/162H646T
16-Bit Registered Transceivers
7
PS2039B 02/24/99
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PI74FCT16646T Switching Characteristics over Operating Range
16646T
16646AT
16646CT
16646DT
16646ET
Com.
Com.
Com.
Com.
Com.
Parameters
Description
Conditions
(1)
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
t
PLH
Propagation Delay
C
L
= 50 pF
2.0
9.0
2.0
6.3
1.5
5.4
1.5
4.4
1.5
3.8
ns
t
PHL
Bus to Bus
R
L
= 500
t
PZH
Output Enable Time
2.0
14.0
2.0
9.8
1.5
7.8
1.5
5.0
1.5
4.8
ns
t
PZL
xDIR or xOE to Bus
t
PHZ
Output Disable Time
(3)
2.0
9.0
2.0
6.3
1.5
6.3
1.5
4.3
1.5
4.0
ns
t
PLZ
xDIR or xOE to Bus
t
PLH
Propagation Delay
2.0
9.0
2.0
6.3
1.5
5.7
1.5
4.4
1.5
3.8
ns
t
PHL
Clock to Bus
t
PLH
Propagation Delay
2.0
11.0
2.0
7.7
1.5
6.2
1.5
5.0
1.5
4.2
ns
t
PHL
xSBA or xSAB to Bus
t
SU
Setup Time HIGH or
4.0
--
2.0
--
2.0
--
2.0
--
2.0
--
ns
LOW, B
US
to Clock
t
H
Hold Time HIGH or
2.0
--
1.5
--
1.5
--
1.0
--
0.0
--
ns
LOW, Bus to Clock
t
W
Clock Pulse Width
6.0
--
5.0
--
5.0
--
3.0
--
3.0
--
ns
HIGH or LOW
(3)
t
SK
(o)
Output Skew
(4)
--
0.5
--
0.5
--
0.5
--
0.5
--
0.5
ns
PI74FCT162646T Switching Characteristics over Operating Range
162646T
162646AT
162646CT
162646DT
162646ET
Com.
Com.
Com.
Com.
Com.
Parameters
Description
Conditions
(1)
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
t
PLH
Propagation Delay
C
L
= 50 pF
2.0
9.0
2.0
6.3
1.5
5.4
1.5
4.4
1.5
3.8
ns
t
PHL
Bus to Bus
R
L
= 500
t
PZH
Output Enable Time
2.0
14.0
2.0
9.8
1.5
7.8
1.5
5.0
1.5
4.8
ns
t
PZL
xDIR or xOE to Bus
t
PHZ
Output Disable Time
(3)
2.0
9.0
2.0
6.3
1.5
6.3
1.5
4.3
1.5
4.0
ns
t
PLZ
xDIR or xOE to Bus
t
PLH
Propagation Delay
2.0
9.0
2.0
6.3
1.5
5.7
1.5
4.4
1.5
3.8
ns
t
PHL
Clock to Bus
t
PLH
Propagation Delay
2.0
11.0
2.0
7.7
1.5
6.2
1.5
5.0
1.5
4.2
ns
t
PHL
xSBA or xSAB to Bus
t
SU
Setup Time HIGH or
4.0
--
2.0
--
2.0
--
2.0
--
2.0
--
ns
LOW, B
US
to Clock
t
H
Hold Time HIGH or
2.0
--
1.5
--
1.5
--
1.0
--
0.0
--
ns
LOW, Bus to Clock
t
W
Clock Pulse Width
6.0
--
5.0
--
5.0
--
3.0
--
3.0
--
ns
HIGH or LOW
(3)
t
SK
(o)
Output Skew
(4)
--
0.5
--
0.5
--
0.5
--
0.5
--
0.5
ns
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
PI74FCT16646T/162646T/162H646T
16-Bit Registered Transceivers
8
PS2039B 02/24/99
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PI74FCT162H646T Switching Characteristics over Operating Range
162H646T
162H646AT 162H646CT 162H646DT 162H646ET
Com.
Com.
Com.
Com.
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Parameters
Description
Conditions
(1)
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
t
PLH
Propagation Delay
C
L
= 50 pF
2.0
9.0
2.0
6.3
1.5
5.4
1.5
4.4
1.5
3.8
ns
t
PHL
Bus to Bus
R
L
= 500
t
PZH
Output Enable Time
2.0
14.0
2.0
9.8
1.5
7.8
1.5
5.0
1.5
4.8
ns
t
PZL
xDIR or xOE to Bus
t
PHZ
Output Disable Time
(3)
2.0
9.0
2.0
6.3
1.5
6.3
1.5
4.3
1.5
4.0
ns
t
PLZ
xDIR or xOE to Bus
t
PLH
Propagation Delay
2.0
9.0
2.0
6.3
1.5
5.7
1.5
4.4
1.5
3.8
ns
t
PHL
Clock to Bus
t
PLH
Propagation Delay
2.0
11.0
2.0
7.7
1.5
6.2
1.5
5.0
1.5
4.2
ns
t
PHL
xSBA or xSAB to Bus
t
SU
Setup Time HIGH or
4.0
--
2.0
--
2.0
--
2.0
--
2.0
--
ns
LOW, B
US
to Clock
t
H
Hold Time HIGH or
2.0
--
1.5
--
1.5
--
1.0
--
0.0
--
ns
LOW, Bus to Clock
t
W
Clock Pulse Width
6.0
--
5.0
--
5.0
--
3.0
--
3.0
--
ns
HIGH or LOW
(3)
t
SK
(o)
Output Skew
(4)
--
0.5
--
0.5
--
0.5
--
0.5
--
0.5
ns
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
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