1
PS2081C 06/08/98
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Logic Block Diagram
1
OE
1
LE
1
O
0
C
D
1
D
0
TO 7 OTHER CHANNELS
2
OE
2
LE
2
O
0
C
D
2
D
0
TO 7 OTHER CHANNELS
Product Features:
V
CC
= 5V 10%
Balanced output drivers:
12 mA
Output impedance:
35
(typical)
Typical V
OLP
(Output Ground Bounce) < 0.5V
at V
CC
= 5V, T
A
= 25C
Bus Hold retains last active bus state during tri-state
Hysteresis on all inputs
Packages available:
48-pin 240 mil wide plastic TSSOP (A)
48-pin 300 mil wide plastic SSOP (V)
48-pin 150 mil wide plastic BQSOP (B)
Device models available on request
Product Description:
Pericom Semiconductor's PI74FCT series of logic circuits are pro-
duced in the Company's advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
The PI74FCT162Q373T is a 16-bit transparent latch designed with 3-
state outputs and are intended for bus oriented applications. The
Output Enable and Latch Enable controls are organized to operate
as two 8-bit latches or one 16-bit latch. When Latch Enable (LE) is
HIGH, the flip-flops appear transparent to the data. The data that
meets the set-up time when LE is LOW is latched. When OE is HIGH,
the bus output is in the high impedance state.
The PI74FCT162Q373T is designed with current limiting resistors at
its outputs to control the output edge rate resulting in lower ground
bounce and undershoot. This device features a typical output
impedance of 35
eliminating the need for external terminating
resistors for most bus interface applications. This noise suppression
benefit is designated by the letter "Q" (for quiet) in the part number.
The PI74FCT162Q373T has "Bus Hold" which retains the input's last
state whenever the input goes to high-impedance preventing
"floating" inputs and eliminating the need for pull-up/down resistors.
PI74FCT162Q373T
Fast Low Noise CMOS 16-Bit
Transparent Latches
PI74FCT162Q373T
LOW NOISE 16-BIT TRANSPARENT LATCHES
2
PS2081C 06/08/98
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Product Pin Description
Pin Name
Description
xOE
Output Enable Inputs (Active LOW)
xLE
Latch Enable Inputs (Active HIGH)
xDx
Inputs
(1)
xOx
3-State Outputs
GND
Ground
V
CC
Power
Inputs
(1)
Outputs
(1)
X
D
X
X
OE
xLE
xOx
H
L
H
H
L
L
H
L
X
H
X
Z
Truth Table
Note:
1. H = High Voltage Level
X = Don't Care L = Low Voltage Level
Z = High Impedance
1
2
3
4
5
6
7
8
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
32
31
30
29
28
27
26
25
1
OE
1
O
0
1
O
1
GND
1
O
2
1
O
3
V
CC
1
O
4
1
O
5
GND
1
O
6
1
O
7
2
O
0
2
O
1
GND
2
O
2
2
O
3
V
CC
2
O
4
2
O
5
GND
2
O
6
2
O
7
2
OE
48-PIN
V48
A48
B48
1
LE
1
D
0
1
D
1
GND
1
D
2
1
D
3
V
CC
1
D
4
1
D
5
GND
1
D
6
1
D
7
2
D
0
2
D
1
GND
2
D
2
2
D
3
V
CC
2
D
4
2
D
5
GND
2
D
6
2
D
7
2
LE
Product Pin Configuration
Note:
1. For the PI74FCT162Q373T, these pins have "Bus
Hold". All other pins are standard, outputs, or I/Os.
PI74FCT162Q373T
LOW NOISE 16-BIT TRANSPARENT LATCHES
3
PS2081C 06/08/98
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
DC Electrical Characteristics
(Over the Operating Range, T
A
= 40C to +85C, V
CC
= 5.0V 10%)
Parameters Description
Test Conditions
(1)
Min.
Typ
(2)
Max.
Units
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH Level
2.0
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW Level
0.8
V
I
IH
Input HIGH Current
Standard Input
(4)
, V
CC
= Max.
V
IN
= V
CC
1
A
I
IH
Input HIGH Current
Bus Hold Input
(5)
, V
CC
= Max.
V
IN
= V
CC
100
A
I
IL
Input LOW Current
Standard Input
(4)
, V
CC
= Min.
V
IN
= GND
1
A
I
IL
Input LOW Current
Bus Hold Input
(5)
, V
CC
= Min.
V
IN
= GND
100
A
I
BHH
Bus Hold
Bus Hold Input
(5)
, V
CC
= Min.
V
IN
= 2.0V
50
A
I
BHL
Sustain Current
V
IN
= 0.8V
+50
I
OZH
High Impedance
V
CC
= Max.
V
OUT
= 2.7V
1
A
I
OZL
Output Current
V
CC
= Max.
V
OUT
= 0.5V
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18 mA
0.7
1.2
V
I
O
Output Drive Current
V
CC
= Max.
(3)
, V
OUT
= 2.5V
50
180
mA
V
H
Input Hysteresis
100
mV
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................................................... 65C to +150C
Ambient Temperature with Power Applied .................................... 40C to +85C
Supply Voltage to Ground Potential (Inputs & Vcc Only) .............. 0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) ........... 0.5V to +7.0V
DC Input Voltage ............................................................................ 0.5V to +7.0V
DC Output Current ..................................................................................... 120 mA
Power Dissipation .......................................................................................... 1.0W
Note:
Stresses greater than those listed under
MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect reliability.
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is 5 A at T
A
= 55C.
5. Pins with Bus Hold are identified in the pin description.
6. This specification does not apply to bi-directional functionalities with Bus Hold.
PI74FCT162Q373T
LOW NOISE 16-BIT TRANSPARENT LATCHES
4
PS2081C 06/08/98
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Output Drive Characteristics
(Over the Operating Range)
Parameters Description
Test Conditions
(1)
Min.
Typ
(2)
Max.
Units
I
ODL
Output LOW Current
V
CC
= 5V, V
IN
= V
IH
OR
V
IL
, V
OUT
= 1.5V
(3)
36
--
--
mA
I
ODH
Output HIGH Current
V
CC
= 5V, V
IN
= V
IH
OR
V
IL
, V
OUT
= 1.5V
(3)
100
166
200
mA
Output Drive Characteristics
(Over the Operating Range)
Parameters
Description
Test Conditions
(1)
Min.
Typ
(2)
Max.
Units
V
OH
Output HIGH Voltage
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OH
= 12.0 mA
2.4
3.3
--
V
V
OL
Output LOW Voltage
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OL
= 12 mA
--
0.3
0.55
V
Notes:
1. For Max. or Min. condtions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is determined by device characterization but is not production tested.
Capacitance
(T
A
= 25C, f = 1 MHz)
Parameters
(4)
Description
Test Conditions
Typ
Max.
Units
C
IN
Input Capacitance
V
IN
= 0V
4.5
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
5.5
8
pF
PI74FCT162Q373T
LOW NOISE 16-BIT TRANSPARENT LATCHES
5
PS2081C 06/08/98
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Power Supply Characteristics
Parameters Description
Test Conditions
(1)
Min.
Typ
(2)
Max.
Units
I
CC
Quiescent Power
V
CC
= Max.
V
IN
= GND or V
CC
0.1
500
A
Supply Current
I
CC
Supply Current per
V
CC
= Max.
V
IN
= 3.4V
(3)
0.5
1.5
mA
Input @ TTL HIGH
I
CCD
Supply Current per
V
CC
= Max.,
V
IN
= V
CC
60
100
A/
Input per MHz
(4)
Outputs Open
V
IN
= GND
MHz
X
OE = GND,
X
LE = V
CC
One Bit Toggling
50% Duty Cycle
I
C
Total Power Supply
V
CC
= Max.,
V
IN
= V
CC
0.6
1.5
(5)
mA
Current
(6)
Outputs Open
V
IN
= GND
f
I
= 10 MH
Z
50% Duty Cycle
X
OE = GND,
X
LE = V
CC
One Bit Toggling
V
IN
= 3.4V
0.9
2.3
(5)
V
IN
= GND
V
CC
= Max.,
V
IN
= V
CC
2.5
5.5
(5)
Outputs Open
V
IN
= GND
f
I
= 2.5 MH
Z
50% Duty Cycle
X
OE = GND,
X
LE = V
CC
16 Bits Toggling
V
IN
= 3.4V
6.4
16.5
(5)
V
IN
= GND
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 5.0V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. I
C
=I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
I
N
I
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
I
= Input Frequency
N
I
= Number of Inputs at f
I
All currents are in milliamps and all frequencies are in megahertz.
PI74FCT162Q373T
LOW NOISE 16-BIT TRANSPARENT LATCHES
6
PS2081C 06/08/98
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
s
r
e
t
e
m
a
r
a
P
n
o
it
p
i
r
c
s
e
D
s
n
o
it
i
d
n
o
C
T
3
7
3
Q
2
6
1
T
A
3
7
3
Q
2
6
1
T
C
3
7
3
Q
2
6
1
T
D
3
7
3
Q
2
6
1
T
E
3
7
3
Q
2
6
1
ti
n
U
.
m
o
C
.
m
o
C
.
m
o
C
.
m
o
C
.
m
o
C
n
i
M
x
a
M
n
i
M
x
a
M
n
i
M
x
a
M
n
i
M
x
a
M
n
i
M
x
a
M
t
PLH
t
PHL
y
a
l
e
D
n
o
it
a
g
a
p
o
r
P
x
O
x
o
t
x
D
x
C
L
= 0
5
P
F
1
R =
0
0
5
5
.
1
0
.
8
5
.
1
5
.
6
5
.
1
2
.
5
5
.
1
2
.
4
5
.
1
4
.
3
s
n
t
PLH
t
PHL
y
a
l
e
D
n
o
it
a
g
a
p
o
r
P
x
O
x
o
t
E
L
x
0
.
2
0
.
3
1
0
.
2
5
.
8
0
.
2
5
.
5
5
.
1
0
.
4
5
.
1
7
.
3
t
PZH
t
PZL
e
m
i
T
e
l
b
a
n
E
t
u
p
t
u
O
x
O
x
o
t
E
O
x
5
.
1
0
.
2
1
5
.
1
5
.
6
5
.
1
5
.
5
5
.
1
8
.
4
5
.
1
8
.
4
t
PHZ
t
PLZ
e
m
i
T
e
l
b
a
si
D
t
u
p
t
u
O
)
3
(
x
O
x
o
t
E
O
x
5
.
1
5
.
7
5
.
1
5
.
5
5
.
1
0
.
5
5
.
1
0
.
4
5
.
1
0
.
4
t
SU
e
m
i
T
e
l
b
a
si
D
t
u
p
t
u
O
E
L
x
o
t
x
D
x
,
W
O
L
0
.
2
-
0
.
2
-
0
.
2
-
5
.
1
-
0
.
1
-
t
H
r
o
H
G
I
H
e
m
it
d
l
o
H
E
L
x
o
t
x
D
x
,
W
O
L
5
.
1
-
5
.
1
-
5
.
1
-
0
.
1
-
0
.
1
-
t
W
h
t
d
i
W
e
sl
u
P
E
L
x
H
G
I
H
)
3
(
0
.
6
-
0
.
5
-
0
.
5
-
0
.
3
-
0
.
3
-
t
SK
(
O
)
w
e
k
S
t
u
o
t
u
O
)
4
(
-
5
.
0
-
5
.
0
-
5
.
0
-
5
.
0
-
5
.
0
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
Switching Characteristics over Operating Range
PDF 
ZIP