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Электронный компонент: PI74FCT2652TQ

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1
PS2022A 03/11/96
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PI74FCT646/648/651/652T
(25
Series) P174FCT2646T/2652T
OCTAL REGISTERED TRANSCEIVERS
Product Description:
Pericom Semiconductor's PI74FCT series of logic circuits are
produced in the Company's advanced 0.6/0.8 micron CMOS
technology, achieving industry leading speed grades. All
PI74FCT2XXX devices have a built-in 25-ohm series resistor on
all outputs to reduce noise because of reflections, thus eliminating
the need for an external terminating resistor.
The PI74FCT646T/648T/651T/652T and PI74FCT2646T/2652T
are designed with a bus transceiver with 3-state D-type flip-flops
and control circuitry arranged for multiplexed transmission of data
directly from the data bus or from the internal storage registers. The
PI74FCT651/652T/2652T utilize GAB and GBA signals to control
the transceiver functions. The PI74FCT646/2646T/648T utilize
the enable control (G) and direction pins (DIR) to control the
transceiver functions. SAB and SBA control pins are used to select
either real-time or stored data transfer. The circuitry used for select
control will eliminate the typical decoding glitch that occurs in a
multiplexer during the transition between real-time and stored data.
A low input level selects real-time data and a high selects stored
data.
The PI74FCT646T is a non-inverting option of the PI74FCT648T.
The PI74FCT652T is a non-inverting option of the PI74FCT651T.
Fast CMOS Octal Registered Transceivers
Logic Block Diagram
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PI74FCT646T/648T/651T/652T
(25
Series PI74FCT2646T/2652T
Product Features:
PI74FCT646T/648T/651T/652T/2646T/2652T is pin compatible
with bipolar FASTTM Series at a higher speed and lower power
consumption
25
series resistor on all outputs (FCT2XXX only)
TTL input and output levels
Low ground bounce outputs
Extremely low static power
Hysteresis on all inputs
Industrial operating temperature range: 40C to +85C
Packages available:
24-pin 300 mil wide plastic DIP (P)
24-pin 150 mil wide plastic QSOP (Q)
24-pin 150 mil wide plastic TQSOP (R)
24-pin 300 mil wide plastic SOIC (S)
Device models available upon request
0D
CPAB
C
0
CPBA
SBA
DIR
G
SAB
0D
C
0
A REG
B REG
B
0
A
0
1 OR 8 CHANNELS
TO 7 OTHER CHANNELS
GBA
GAB
PI74FCT651/652 ONLY
PI74FCT651/652 ONLY
646/652
ONLY
646/652
ONLY
PI74FCT646/648
ONLY
2
PS2022A 03/11/96
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PI74FCT646/648/651/652T
(25
Series) P174FCT2646T/2652T
OCTAL REGISTERED TRANSCEIVERS
Pin Name
Description
A
0
-A
7
Data Register A Inputs
Data Register B Outputs
B
0
-B
7
Data Register B Inputs
Data Register A Outputs
CPAB, CPBA
Clock Pulse Inputs
SAB, SBA
Output Data Source Select Inputs
DIR, G
Output Enable Inputs
(646/648/2646)
GAB, GBA
Output Enable Inputs
(651/652/2652)
GND
Ground
V
CC
Power
Product Pin Description
PI74FCT646/648T
Product Pin Configuration
PI74FCT651/652T
Product Pin Configuration
PI74FCT646/2646T
PI74FCT648T
Inputs
DATA I/O
(2)
Function/Operation
Function/Operation
G
DIR
CPAB CPBA SAB
SBA
A0-A7
B0-B7
Isolation
Isolation
H
X
H or L
H or L
X
X
Input
Input
Store A and B Data
Store A and B Data
H
X
X
X
Real Time B Data to A Bus
Real Time B Data to A Bus
L
L
X
X
X
L
Output
Input
Stored B Data to A Bus
Stored B Data to A Bus
L
L
X
H or L
X
H
Real Time A Data to B Bus
Real Time A Data to B Bus
L
H
X
X
L
X
Input
Output
Stored A Data to B Bus
Stored A Data to B Bus
L
H
H or L
X
H
X
PI74FCT646/648/2646T Truth Table
PI74FCT651T
PI74FCT652/2652T
Inputs
DATA I/O
(2)
Function/Operation
Function/Operation
GAB
GBA
CPAB CPBA SAB
SBA
A0-A7
B0-B7
Isolation
Isolation
L
H
H or L
H or L
X
X
Input
Input
Store A and B Data
Store A and B Data
L
H
X
X
Store A, Hold B
Store A, Hold B
X
H
H or L
X
X
Input
Unspecified
(1)
Store A in Both Registers
(3)
Store A in Both Registers
H
H
X
(2)
X
Input
Output
Hold A, Store B
Hold A, Store B
L
X
H or L
X
X
Unspecified
(1)
Input
Store B in Both Registers
(4)
Store B in Both Registers
L
L
X
X
(2)
Output
Input
Real Time B Data to A Bus
Real Time B Data to A Bus
L
L
X
X
X
L
Output
Input
Stored B Data to A Bus
Stored B Data to A Bus
L
L
X
H or L
X
H
Real Time A Data to B Bus
Real Time A Data to B Bus
H
H
X
X
L
X
Input
Output
Stored A Data to B Bus
Stored A Data to B Bus
H
H
H or L
X
H
X
Stored A Data to B Bus and Stored A Data to B Bus and
H
L
H or L
H or L
H
H
Output
Output
Stored B Data to A Bus
Stored B Data to A Bus
PI74FCT651/652/2652T Truth Table
1.
The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data
input functions are always enabled, i.e., data at the bus pins will be stored on every low-to-high transition
on the clock inputs.
2.
Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered in order to load both registers.
3.
A in B Register
4.
B in A Register
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CPAB
SAB
DIR
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
GND
Vcc
CPBA
SBA
G
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
24-PIN
P24
Q24
R24
S24
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CPAB
SAB
GAB
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
GND
Vcc
CPBA
SBA
GBA
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
24-PIN
P24
Q24
R24
S24
3
PS2022A 03/11/96
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PI74FCT646/648/651/652T
(25
Series) P174FCT2646T/2652T
OCTAL REGISTERED TRANSCEIVERS
REAL-TIME TRANSFER
BUS B TO A
646/648/
DIR
G
CPAB CPBA
SAB
SBA
2646
L
L
X
X
X
L
651/652/
GAB GBA CPAB CPBA
SAB
SBA
2652
L
L
X
X
X
L
REAL-TIME TRANSFER
BUS A TO B
646/648/
DIR
G
CPAB CPBA
SAB
SBA
2646
H
L
X
X
L
X
651/652/
GAB GBA CPAB CPBA
SAB
SBA
2652
H
H
X
X
L
X
STORAGE FROM
A AND/OR B
TRANSFER STORES
DATA TO A AND/OR B
646/648/
DIR
G
CPAB CPBA
SAB
SBA
2646
H
L
X
X
X
L
L
X
X
X
X
H
X
X
651/652/
GAB GBA CPAB CPBA
SAB
SBA
2652
X
H
X
X
X
L
X
X
X
X
L
H
X
X
646/648
(1)
DIR
G
CPAB CPBA
SAB
SBA
2646
L
L
X
H or L
X
H
H
L
H or L
X
H
X
651/652/
GAB GBA CPAB CPBA
SAB
SBA
2652
H
L
H or L
H or L
H
H
1. Note: The FCT646/2646 cannot transfer data to
A bus and B bus simultaneously.
BUS
A
BUS
B
BUS
A
BUS
B
BUS
A
BUS
B
BUS
A
BUS
B
4
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PI74FCT646/648/651/652T
(25
Series) P174FCT2646T/2652T
OCTAL REGISTERED TRANSCEIVERS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................................................. 65C to +150C
Ambient Temperature with Power Applied ................................. -40C to +85C
Supply Voltage to Ground Potential (Inputs & Vcc Only) .......... 0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) ....... 0.5V to +7.0V
DC Input Voltage ......................................................................... 0.5V to +7.0V
DC Output Current ................................................................................... 120 mA
Power Dissipation ......................................................................................... 0.5W
Note:
Stresses greater than those listed under
MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect reliability.
DC Electrical Characteristics
(Over the Operating Range, T
A
= 40C to +85C, V
CC
= 5.0V 5%)
Parameters Description
Test Conditions
(1)
Min. Typ
(2)
Max. Units
V
OH
Output HIGH Voltage
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OH
= 15.0 mA
2.4
3.0
V
V
OL
Output LOW Current
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OL
= 64 mA
0.3
0.55
V
V
OL
Output LOW Current
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OL
= 12 mA (25
Series)
0.3
0.50
V
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH Level
2.0
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW Level
0.8
V
I
IH
Input HIGH Current
V
CC
= Max.
V
IN
= V
CC
1
A
I
IL
Input LOW Current
V
CC
= Max.
V
IN
= GND
1
A
I
OZH
High Impedance
V
CC
= M
AX
.
V
OUT
= 2.7V
1
A
I
OZL
Output Current
V
OUT
= 0.5V
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18 mA
0.7
1.2
V
I
OFF
Power Down Disable
V
CC
= GND, V
OUT
= 4.5V
--
--
100
A
I
OS
Short Circuit Current
V
CC
= Max.
(3)
, V
OUT
= GND
60
120
mA
V
H
Input Hysteresis
200
mV
Capacitance
(T
A
= 25C, f = 1 MHz)
Parameters
(4)
Description
Test Conditions
Typ
Max.
Units
C
IN
Input Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
12
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is determined by device characterization but is not production tested.
5
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PI74FCT646/648/651/652T
(25
Series) P174FCT2646T/2652T
OCTAL REGISTERED TRANSCEIVERS
Power Supply Characteristics
Parameters Description
Test Conditions
(1)
Min.
Typ
(2)
Max.
Units
I
CC
Quiescent Power
V
CC
= Max.
V
IN
= GND
0.1
500
A
Supply Current
or V
CC
I
CC
Supply Current per
V
CC
= Max.,
V
IN
= 3.4V
(3)
0.5
2.0
mA
Input @ TTL HIGH
I
CCD
Supply Current per
V
CC
= Max.,
V
IN
= V
CC
0.15
0.25
mA/
Input per MHz
(4)
Outputs Open
V
IN
= GND
MHz
G = DIR = GND or
GAB = GBA = GND
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply
V
CC
= Max.,
V
IN
= V
CC
1.5
3.5
(5)
mA
Current
(6)
Outputs Open
V
IN
= GND
f
CP
= 10 MH
Z
50% Duty Cycle
V
IN
= 3.4V
2.0
5.5
(5)
G = DIR = GND or
V
IN
= GND
GAB = GBA = GND
f
I
= 5 MH
Z
One Bit Toggling
V
CC
= Max.,
V
IN
= V
CC
3.8
7.3
(5)
Outputs Open
V
IN
= GND
f
CP
= 10 MH
Z
50% Duty Cycle
V
IN
= 3.4V
6.0
16.3
(5)
G = DIR = GND or
V
IN
= GND
GAB = GBA = GND
Eight Bits Toggling
f
I
= 2.5 MH
Z
50% Duty Cycle
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 5.0V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. I
C
=I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
I
N
I
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
I
= Input Frequency
N
I
= Number of Inputs at f
I
All currents are in milliamps and all frequencies are in megahertz.
6
PS2022A 03/11/96
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PI74FCT646/648/651/652T
(25
Series) P174FCT2646T/2652T
OCTAL REGISTERED TRANSCEIVERS
PI74FCT646/2646T Switching Characteristics over Operating Range
646T/2646T
646AT/2646AT
646CT
646DT
Com.
Com.
Com.
Com.
Parameters
Description
Conditions
(1)
Min
Max
Min
Max
Min
Max
Min
Max
Unit
t
PLH
Propagation Delay
C
L
= 50 pF
2.0
7.5
2.0
6.3
1.5
5.4
1.5
4.8
ns
t
PHL
Bus to Bus
R
L
= 500
t
PZH
Output Enable Time
2.0
14.0
2.0
9.8
1.5
7.8
1.5
7.3
ns
t
PZL
G, DIR to Bus
t
PHZ
Output Disable Time
(3)
2.0
9.0
2.0
6.3
1.5
6.3
1.5
6.3
ns
t
PLZ
G, DIR to Bus
t
PLH
Propagation Delay
2.0
9.0
2.0
6.3
1.5
5.7
1.5
5.2
ns
t
PHL
Clock to Bus
t
PLH
Propagation Delay
2.0
9.5
2.0
7.7
1.5
6.2
1.5
5.8
ns
t
PHL
SBA or SAB to Bus
t
SU
Setup Time HIGH or
4.0
--
2.0
--
2.0
--
2.0
--
ns
LOW, B
US
to Clock
t
H
Hold Time HIGH or
2.0
--
1.5
--
1.5
--
1.5
--
ns
LOW, Bus to Clock
t
W
Clock Pulse Width
(3)
6.0
--
5.0
--
5.0
--
5.0
--
ns
HIGH or LOW
PI74FCT648T Switching Characteristics over Operating Range
648T
648AT
648CT
648DT
Com.
Com.
Com.
Com.
Parameters
Description
Conditions
(1)
Min
Max
Min
Max
Min
Max
Min
Max
Unit
t
PLH
Propagation Delay
C
L
= 50 pF
2.0
7.5
2.0
6.3
1.5
5.4
1.5
4.8
ns
t
PHL
Bus to Bus
R
L
= 500
t
PZH
Output Enable Time
2.0
14.0
2.0
9.8
1.5
7.8
1.5
7.3
ns
t
PZL
G, DIR to Bus
t
PHZ
Output Disable Time
(3)
2.0
9.0
2.0
6.3
1.5
6.3
1.5
6.3
ns
t
PLZ
G, DIR to Bus
t
PLH
Propagation Delay
2.0
9.0
2.0
6.3
1.5
5.7
1.5
5.2
ns
t
PHL
Clock to Bus
t
PLH
Propagation Delay
2.0
9.5
2.0
7.7
1.5
6.2
1.5
5.8
ns
t
PHL
SBA or SAB to Bus
t
SU
Setup Time HIGH or
4.0
--
2.0
--
2.0
--
2.0
--
ns
LOW, B
US
to Clock
t
H
Hold Time HIGH or
2.0
--
1.5
--
1.5
--
1.5
--
ns
LOW, Bus to Clock
t
W
Clock Pulse Width
(3)
6.0
--
5.0
--
5.0
--
5.0
--
ns
HIGH or LOW
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter guaranteed but not production tested.
7
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PI74FCT646/648/651/652T
(25
Series) P174FCT2646T/2652T
OCTAL REGISTERED TRANSCEIVERS
PI74FCT652/2652T Switching Characteristics over Operating Range
652T/2652T
652AT/2652AT
652CT
652DT
Com.
Com.
Com.
Com.
Parameters
Description
Conditions
(1)
Min
Max
Min
Max
Min
Max
Min
Max
Unit
t
PLH
Propagation Delay
C
L
= 50 pF
2.0
9.0
2.0
6.3
1.5
5.4
1.5
4.8
ns
t
PHL
Bus to Bus
R
L
= 500
t
PZH
Output Enable Time
2.0
12.5
2.0
9.8
1.5
7.8
1.5
7.3
ns
t
PZL
GBA, GAB to Bus
t
PHZ
Output Disable Time
(3)
2.0
9.0
2.0
6.3
1.5
6.3
1.5
6.0
ns
t
PLZ
GBA, GAB to Bus
t
PLH
Propagation Delay
2.0
9.0
2.0
6.3
1.5
5.7
1.5
5.2
ns
t
PHL
Clock to Bus
t
PLH
Propagation Delay
2.0
9.5
2.0
7.7
1.5
6.2
1.5
5.8
ns
t
PHL
SBA or SAB to Bus
t
SU
Setup Time HIGH or
4.0
--
2.0
--
2.0
--
2.0
--
ns
LOW, B
US
to Clock
t
H
Hold Time HIGH or
2.0
--
1.5
--
1.5
--
1.5
--
ns
LOW, Bus to Clock
t
W
Clock Pulse Width
(3)
6.0
--
5.0
--
5.0
--
5.0
--
ns
HIGH or LOW
PI74FCT651T Switching Characteristics over Operating Range
651T
651AT
651CT
651DT
Com.
Com.
Com.
Com.
Parameters
Description
Conditions
(1)
Min
Max
Min
Max
Min
Max
Min
Max
Unit
t
PLH
Propagation Delay
C
L
= 50 pF
2.0
9.0
2.0
6.3
1.5
5.4
1.5
4.8
ns
t
PHL
Bus to Bus
R
L
= 500
t
PZH
Output Enable Time
2.0
12.5
2.0
9.8
1.5
7.8
1.5
7.3
ns
t
PZL
GBA, GAB to Bus
t
PHZ
Output Disable Time
(3)
2.0
9.0
2.0
6.3
1.5
6.3
1.5
6.0
ns
t
PLZ
GBA, GAB to Bus
t
PLH
Propagation Delay
2.0
9.0
2.0
6.3
1.5
5.7
1.5
5.2
ns
t
PHL
Clock to Bus
t
PLH
Propagation Delay
2.0
9.5
2.0
7.7
1.5
6.2
1.5
5.8
ns
t
PHL
SBA or SAB to Bus
t
SU
Setup Time HIGH or
4.0
--
2.0
--
2.0
--
2.0
--
ns
LOW, B
US
to Clock
t
H
Hold Time HIGH or
2.0
--
1.5
--
1.5
--
1.5
--
ns
LOW, Bus to Clock
t
W
Clock Pulse Width
(3)
6.0
--
5.0
--
5.0
--
5.0
--
ns
HIGH or LOW
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com