ChipFind - документация

Электронный компонент: PI74FCT2823TR

Скачать:  PDF   ZIP
1
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI74FCT821T/823T/825T
(25
Series) P174FCT2821T/2823T
BUS INTERFACE REGISTERS
PS2023A 03/11/96
Product Description:
Pericom Semiconductor's PI74FCT series of logic circuits are
produced in the Company's advanced 0.8 micron CMOS
technology, achieving industry leading speed grades. All
PI74FCT2XXX devices have a built-in 25-ohm series resistor on
all outputs to reduce noise because of reflections, thus eliminating
the need for an external terminating resistor.
The PI74FCT821T/2821T is a 10-bit wide register designed with
ten D-type flip-flops with a buffered common clock and buffered
3-state outputs. The PI74FCT823/2823T is a 9-bit wide register
designed with Clock Enable and Clear. The PI74FCT825T is an
8-bit wide register with all PI74FCT823T controls plus multiple
enables. When output enable (OE) is LOW, the outputs are enabled.
When OE is HIGH, the outputs are in the high impedance state.
Input data meeting the setup and hold time requirements of the D
inputs is transferred to the Y outputs on the LOW-to-HIGH transition
of the clock input.
Logic Block Diagram
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Fast CMOS
Bus Interface Registers
Product Features:
PI74FCT821T/823T/825T/2821T/2823T is pin compatible with
bipolar FASTTM Series at a higher speed and lower power
consumption
25
series resistor on all outputs (FCT2XXX only)
TTL input and output levels
Low ground bounce outputs
Extremely low static power
Hysteresis on all inputs
Industrial operating temperature range: 40C to +85C
Packages available:
24-pin 300 mil wide plastic DIP (P)
24-pin 150 mil wide plastic QSOP (Q)
24-pin 150 mil wide plastic TQSOP (R)
24-pin 300 mil wide plastic SOIC (S)
Device models available upon request
PI74FCT821T/823T/825T
(25
Series) PI74FCT2821T/2823T
D
Q
D
0
CLR
CP
CP
OE
Y
0
Q
CL
EN
D
Q
D
1
CP
Y
1
Q
CL
D
Q
D
2
CP
Y
2
Q
CL
D
Q
D
3
CP
Y
3
Q
CL
D
Q
D
4
CP
Y
4
Q
CL
D
Q
D
5
CP
Y
5
Q
CL
D
Q
D
N-1
CP
Y
N-1
Q
CL
D
Q
D
N
CP
Y
N
Q
CL
OE
1
OE
2
OE
3
PI74FCT825 Only
2
PS2023A 03/11/96
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI74FCT821T/823T/825T
(25
Series) P174FCT2821T/2823T
BUS INTERFACE REGISTERS
Pin Name
Description
OE
Output Enable Input (Active LOW)
CP
Clock Pulse for the register. Enters data on
LOW-to-HIGH transition
D
N
Data Inputs
Y
N
3-State Outputs
CLR
Clear Input (Active LOW)
(823/825/2823 Only)
EN
Clock Enable Input (Active LOW)
GND
Ground
V
CC
Power
Product Pin Description
PI74FCT821/2821T Product Pin Configuration
PI74FCT823/2823T Product Pin Configuration
PI74FCT825T Product Pin Configuration
PI74FCT821/823/825/2821/2823T Truth Table
(1)
Inputs
Outputs Internal
Function CLR EN
OE
CP
D
N
Y
N
Q
N
High-Z
H
L
H
L
Z
L
H
L
H
H
Z
H
Clear
L
X
H
X
X
Z
L
L
X
L
X
X
L
L
Hold
H
H
H
X
X
Z
NC
H
H
L
X
X
NC
NC
Load
H
L
H
L
Z
L
H
L
H
H
Z
H
H
L
L
L
L
L
H
L
L
H
H
H
1.
H = High Voltage Level
L = Low Voltage Level
X = Don't Care
Z = High Impedance
NC = No Change
= LOW-to-HIGH transition
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
GND
Vcc
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
CP
24-PIN
P24
Q24
R24
S24
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
CLR
GND
Vcc
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
EN
CP
24-PIN
P24
Q24
R24
S24
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
1
OE
2
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CLR
GND
Vcc
OE
3
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
EN
CP
24-PIN
P24
Q24
R24
S24
3
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI74FCT821T/823T/825T
(25
Series) P174FCT2821T/2823T
BUS INTERFACE REGISTERS
PS2023A 03/11/96
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................................................. 65C to +150C
Ambient Temperature with Power Applied ................................. -40C to +85C
Supply Voltage to Ground Potential (Inputs & Vcc Only) .......... 0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) ....... 0.5V to +7.0V
DC Input Voltage ......................................................................... 0.5V to +7.0V
DC Output Current ................................................................................... 120 mA
Power Dissipation ......................................................................................... 0.5W
Note:
Stresses greater than those listed under
MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect reliability.
DC Electrical Characteristics
(Over the Operating Range, T
A
= 40C to +85C, V
CC
= 5.0V 5%)
Parameters Description
Test Conditions
(1)
Min. Typ
(2)
Max. Units
V
OH
Output HIGH Voltage
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OH
= 15.0 mA
2.4
3.0
V
V
OL
Output LOW Current
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OL
= 48 mA
0.3
0.50
V
V
OL
Output LOW Current
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OL
= 12 mA (25
Series)
0.3
0.50
V
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH Level
2.0
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW Level
0.8
V
I
IH
Input HIGH Current
V
CC
= Max.
V
IN
= V
CC
1
A
I
IL
Input LOW Current
V
CC
= Max.
V
IN
= GND
1
A
I
OZH
High Impedance
V
CC
= M
AX
.
V
OUT
= 2.7V
1
A
I
OZL
Output Current
V
OUT
= 0.5V
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18 mA
0.7
1.2
V
I
OFF
Power Down Disable
V
CC
= GND, V
OUT
= 4.5V
--
--
100
A
I
OS
Short Circuit Current
V
CC
= Max.
(3)
, V
OUT
= GND
60
120
mA
V
H
Input Hysteresis
200
mV
Capacitance
(T
A
= 25C, f = 1 MHz)
Parameters
(4)
Description
Test Conditions
Typ
Max.
Units
C
IN
Input Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
12
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is determined by device characterization but is not production tested.
4
PS2023A 03/11/96
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI74FCT821T/823T/825T
(25
Series) P174FCT2821T/2823T
BUS INTERFACE REGISTERS
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 5.0V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. I
C
=I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
I
N
I
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4 V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
I
= Input Frequency
N
I
= Number of Inputs at f
I
All currents are in milliamps and all frequencies are in megahertz.
Power Supply Characteristics
Parameters Description
Test Conditions
(1)
Min.
Typ
(2)
Max.
Units
I
CC
Quiescent Power
V
CC
= Max.
V
IN
= GND
0.1
500
A
Supply Current
or V
CC
I
CC
Supply Current per
V
CC
= Max.
V
IN
= 3.4V
(3)
0.5
2.0
mA
Input @ TTL HIGH
I
CCD
Supply Current per
V
CC
= Max.,
V
IN
= V
CC
0.15
0.25
mA/
Input per MHz
(4)
Outputs Open
V
IN
= GND
MHz
OE = EN = GND
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply
V
CC
= Max.,
V
IN
= V
CC
1.5
3.5
(5)
mA
Current
(6)
Outputs Open
V
IN
= GND
f
CP
= 10 MH
Z
50% Duty Cycle
V
IN
= 3.4V
2.0
5.5
(5)
OE = EN = GND
V
IN
= GND
f
I
= 5 MH
Z
One Bit Toggling
V
CC
= Max.,
V
IN
= V
CC
3.8
7.3
(5)
Outputs Open
V
IN
= GND
f
CP
= 10 MH
Z
50% Duty Cycle
V
IN
= 3.4V
6.0
16.3
(5)
OE = EN = GND
V
IN
= GND
Eight Bits Toggling
f
I
= 2.5 MH
Z
50% Duty Cycle
5
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI74FCT821T/823T/825T
(25
Series) P174FCT2821T/2823T
BUS INTERFACE REGISTERS
PS2023A 03/11/96
PI74FCT821/2821T Switching Characteristics over Operating Range
821AT/2821AT
821BT/2821BT
821CT/2821CT
Com.
Com.
Com.
Parameters
Description
Conditions
(1)
Min
Max
Min
Max
Min
Max
Unit
t
PLH
Propagation Delay
C
L
= 50 pF
1.5
10.0
1.5
7.5
1.5
6.0
ns
t
PHL
CP to Y
N
R
L
= 500
(OE = LOW)
C
L
= 300 pF
(3)
1.5
20.0
1.5
15.0
1.5
12.5
ns
R
L
= 500
t
SU
Setup Time HIGH or
C
L
= 50 pF
4.0
--
3.0
--
3.0
--
ns
LOW, D
N
to CP
R
L
= 500
t
H
Hold Time HIGH or
2.0
--
1.5
--
1.5
--
ns
LOW, D
N
to CP
t
SU
Setup Time HIGH or
4.0
--
3.0
--
3.0
--
ns
LOW, EN to CP
t
H
Hold Time HIGH or
2.0
--
0
--
0
--
ns
LOW, EN to CP
t
PHL
Propagation Delay,
1.5
14.0
1.5
9.0
1.5
8.0
ns
CLR to Y
N
t
REM
Recovery Time,
(3)
6.0
--
6.0
--
6.0
--
ns
CLR to CP
t
W
Clock Pulse Width
(3)
7.0
--
5.0
--
6.0
--
ns
HIGH or LOW
t
W
CLR Pulse Width
(3)
6.0
--
6.0
--
6.0
--
ns
LOW
t
PZH
Output Enable Time
C
L
= 50 pF
1.5
11.5
1.5
8.0
1.5
7.0
ns
t
PZL
OE to Y
N
R
L
= 500
C
L
= 300 pF
(3)
1.5
23.0
1.5
15.0
1.5
12.5
ns
R
L
= 500
t
PHZ
Output Disable Time
(3)
C
L
= 50 pF
1.5
7.0
1.5
6.5
1.5
6.2
ns
t
PLZ
OE to Y
N
R
L
= 500
C
L
= 300 pF
(3)
1.5
8.0
1.5
7.5
1.5
6.5
ns
R
L
= 500
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
6
PS2023A 03/11/96
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI74FCT821T/823T/825T
(25
Series) P174FCT2821T/2823T
BUS INTERFACE REGISTERS
PI74FCT823/2823T Switching Characteristics over Operating Range
823AT/2823AT
823BT/2823BT
823CT/2823CT
Com.
Com.
Com.
Parameters
Description
Conditions
(1)
Min
Max
Min
Max
Min
Max
Unit
t
PLH
Propagation Delay
C
L
= 50 pF
1.5
10.0
1.5
7.5
1.5
6.0
ns
t
PHL
CP to Y
N
R
L
= 500
(OE = LOW)
C
L
= 300 pF
(3)
1.5
20.0
1.5
15.0
1.5
12.5
ns
R
L
= 500
t
SU
Setup Time HIGH or
C
L
= 50 pF
4.0
--
3.0
--
3.0
--
ns
LOW, D
N
to CP
R
L
= 500
t
H
Hold Time HIGH or
2.0
--
1.5
--
1.5
--
ns
LOW, D
N
to CP
t
SU
Setup Time HIGH or
4.0
--
3.0
--
3.0
--
ns
LOW, EN to CP
t
H
Hold Time HIGH or
2.0
--
0
--
0
--
ns
LOW, EN to CP
t
PHL
Propagation Delay,
1.5
13.0
1.5
9.0
1.5
8.0
ns
CLR to Y
N
t
REM
Recovery Time,
(3)
6.0
--
6.0
--
6.0
--
ns
CLR to CP
t
W
Clock Pulse Width
(3)
7.0
--
5.0
--
6.0
--
ns
HIGH or LOW
t
W
CLR Pulse Width
(3)
6.0
--
6.0
--
6.0
--
ns
LOW
t
PZH
Output Enable Time
C
L
= 50 pF
1.5
11.5
1.5
8.0
1.5
7.0
ns
t
PZL
OE to Y
N
R
L
= 500
C
L
= 300 pF
(3)
1.5
23.0
1.5
15.0
1.5
12.5
ns
R
L
= 500
t
PHZ
Output Disable Time
(3)
C
L
= 50 pF
1.5
7.0
1.5
6.5
1.5
6.2
ns
t
PLZ
OE to Y
N
R
L
= 500
C
L
= 300 pF
(3)
1.5
8.0
1.5
7.5
1.5
6.5
ns
R
L
= 500
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
7
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI74FCT821T/823T/825T
(25
Series) P174FCT2821T/2823T
BUS INTERFACE REGISTERS
PS2023A 03/11/96
PI74FCT825T Switching Characteristics over Operating Range
825AT
825BT
825CT
Com.
Com.
Com.
Parameters
Description
Conditions
(1)
Min
Max
Min
Max
Min
Max
Unit
t
PLH
Propagation Delay
C
L
= 50 pF
1.5
10.0
1.5
7.5
1.5
6.0
ns
t
PHL
CP to Y
N
R
L
= 500
(OE = LOW)
C
L
= 300 pF
(3)
1.5
20.0
1.5
15.0
1.5
12.5
ns
R
L
= 500
t
SU
Setup Time HIGH or
C
L
= 50 pF
4.0
--
3.0
--
3.0
--
ns
LOW, D
N
to CP
R
L
= 500
t
H
Hold Time HIGH or
2.0
--
1.5
--
1.5
--
ns
LOW, D
N
to CP
t
SU
Setup Time HIGH or
4.0
--
3.0
--
3.0
--
ns
LOW, EN to CP
t
H
Hold Time HIGH or
2.0
--
0
--
0
--
ns
LOW, EN to CP
t
PHL
Propagation Delay,
1.5
13.0
1.5
9.0
1.5
8.0
ns
CLR to Y
N
t
REM
Recovery Time,
6.0
--
6.0
--
6.0
--
ns
CLR to CP
t
W
Clock Pulse Width
7.0
--
5.0
--
6.0
--
ns
HIGH or LOW
t
W
CLR Pulse Width
(3)
6.0
--
6.0
--
6.0
--
ns
LOW
t
PZH
Output Enable Time
C
L
= 50 pF
1.5
11.5
1.5
8.0
1.5
7.0
ns
t
PZL
OE to Y
N
R
L
= 500
C
L
= 300 pF
(3)
1.5
23.0
1.5
15.0
1.5
12.5
ns
R
L
= 500
t
PHZ
Output Disable Time
(3)
C
L
= 50 pF
1.5
7.0
1.5
6.5
1.5
6.2
ns
t
PLZ
OE to Y
N
R
L
= 500
C
L
= 300 pF
(3)
1.5
8.0
1.5
7.5
1.5
6.5
ns
R
L
= 500
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com