1
PS2025A 03/11/96
PI74FCT841T/843T/845T
(25
(25
(25
(25
(25
S
ERIES
) P174FCT2841T
BUS INTERFACE LATCHES
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Product Description:
Pericom Semiconductor's PI74FCT series of logic circuits are
produced in the Company's advanced 0.8 micron CMOS
technology, achieving industry leading speed grades. All
PI74FCT2XXX devices have a built-in 25-ohm series resistor on
all outputs to reduce noise because of reflections, thus eliminating
the need for an external terminating resistor.
The PI74FCT841T/843T/845T and P174FCT2841T series are
buffered interface latches. These transparent latches designed with
3-state outputs and are designed to eliminate the extra packages
required to buffer existing latches and provide extra data width for
wider address/data paths or buses carrying parity. When Latch
Enable (LE) is HIGH, the flip-flops appear transparent to the data.
The data that meets the set-up time when LE is LOW is latched.
When OE is HIGH, the bus output is in the high impedance state.
The PI74FCT841/2841T is a 10-bit latch, the PI74FCT843T is a
9-bit latch, and the PI74FCT845T is an 8-bit latch.
PI74FCT841/843/845/2842T Logic Block Diagram
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Fast CMOS
Bus Interface Latches
PI74FCT841T/843T/845T
(25
(25
(25
(25
(25
Series) PI74FCT2841T
Product Features:
PI74FCT841/843/845/2841T is pin compatible with bipolar
FASTTM Series at a higher speed and lower power
consumption
25
series resistor on all outputs (FCT2XXX only)
TTL input and output levels
Low ground bounce outputs
Extremely low static power
Hysteresis on all inputs
Industrial operating temperature range: 40C to +85C
Packages available:
24-pin 300 mil wide plastic DIP (P)
24-pin 150 mil wide plastic QSOP (Q)
24-pin 150 mil wide plastic TQSOP (R)
24-pin 300 mil wide plastic SOIC (S)
Q
D
CLR
OE
LE
D
0
Y
0
CLR
PRE
LE
P
Q
D
CLR
D
1
Y
1
LE
P
Q
D
CLR
D
2
Y
2
LE
P
Q
D
CLR
D
3
Y
3
LE
P
Q
D
CLR
D
4
Y
4
LE
P
Q
D
CLR
D
5
Y
5
LE
P
Q
D
CLR
D
N1
Y
N1
LE
P
Q
D
CLR
D
N
Y
N
LE
P
2
PS2025A 03/11/96
PI74FCT841T/843T/845T
(25
(25
(25
(25
(25
S
ERIES
) P174FCT2841T
BUS INTERFACE LATCHES
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Pin Name
Description
Y
N
3-State Latch Outputs
D
N
Latch Data Inputs
LE
Latch Enable Input
OE
Output Enable Control
CLR
Clear Latch
PRE
Preset Latch High, Preset Overrides CLR
GND
Ground
V
CC
Power
Product Pin Description
PI74FCT843T 9-Bit Latch Product Configuration
PI74FCT845T 8-Bit Latch Product Configuration
Truth Table
(1)
Inputs
Outputs Internal
Function
CLR PRE OE
LE
D
N
Y
N
Q
N
High-Z
H
H
H
X
X
Z
X
H
H
H
H
L
Z
L
H
H
H
H
H
Z
H
Latched
(High Z)
H
H
H
L
X
Z
NC
Transparent
H
H
L
H
L
L
L
H
H
L
H
H
H
H
Latched
H
H
L
L
X
NC
NC
Preset
H
L
L
X
X
H
H
Clear
L
H
L
X
X
L
L
Preset
L
L
L
X
X
H
H
Latched
(High Z)
L
H
H
L
X
Z
L
Latched
(High Z)
H
L
H
L
X
Z
H
1.
H = High Voltage Level
L = Low Voltage Level
X = Don't Care
NC = No Change
Z = High Impedance
PI74FCT841/2841T 10-Bit Latch
Product Configuration
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
GND
Vcc
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
LE
24-PIN
P24
Q24
R24
S24
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
CLR
GND
Vcc
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
PRE
LE
24-PIN
P24
Q24
R24
S24
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
1
OE
2
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CLR
GND
Vcc
OE
3
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
PRE
LE
24-PIN
P24
Q24
R24
S24
3
PS2025A 03/11/96
PI74FCT841T/843T/845T
(25
(25
(25
(25
(25
S
ERIES
) P174FCT2841T
BUS INTERFACE LATCHES
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................................................. 65C to +150C
Ambient Temperature with Power Applied ................................. -40C to +85C
Supply Voltage to Ground Potential (Inputs & Vcc Only) .......... 0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) ....... 0.5V to +7.0V
DC Input Voltage ......................................................................... 0.5V to +7.0V
DC Output Current ................................................................................... 120 mA
Power Dissipation ......................................................................................... 0.5W
Note:
Stresses greater than those listed under
MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect reliability.
DC Electrical Characteristics
(Over the Operating Range, T
A
= 40C to +85C, V
CC
= 5.0V 5%)
Parameters Description
Test Conditions
(1)
Min. Typ
(2)
Max. Units
V
OH
Output HIGH Voltage
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OH
= 15.0 mA
2.4
3.0
V
V
OL
Output LOW Current
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OL
= 48 mA
0.3
0.50
V
V
OL
Output LOW Current
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OL
= 12 mA (25
Series)
0.3
0.50
V
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH Level
2.0
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW Level
0.8
V
I
IH
Input HIGH Current
V
CC
= Max.
V
IN
= V
CC
1
A
I
IL
Input LOW Current
V
CC
= Max.
V
IN
= GND
1
A
I
OZH
High Impedance
V
CC
= M
AX
.
V
OUT
= 2.7V
1
A
I
OZL
Output Current
V
OUT
= 0.5V
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18 mA
0.7
1.2
V
I
OFF
Power Down Disable
V
CC
= GND, V
OUT
= 4.5V
--
--
100
A
I
OS
Short Circuit Current
V
CC
= Max.
(3)
, V
OUT
= GND
60
120
mA
V
H
Input Hysteresis
200
mV
Capacitance
(T
A
= 25C, f = 1 MHz)
Parameters
(4)
Description
Test Conditions
Typ
Max.
Units
C
IN
Input Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
12
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is determined by device characterization but is not production tested.
4
PS2025A 03/11/96
PI74FCT841T/843T/845T
(25
(25
(25
(25
(25
S
ERIES
) P174FCT2841T
BUS INTERFACE LATCHES
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Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 5.0V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. I
C
=I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
I
N
I
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
I
= Input Frequency
N
I
= Number of Inputs at f
I
All currents are in milliamps and all frequencies are in megahertz.
Power Supply Characteristics
Parameters Description
Test Conditions
(1)
Min.
Typ
(2)
Max.
Units
I
CC
Quiescent Power
V
CC
= Max.
V
IN
= GND
0.1
500
A
Supply Current
or V
CC
I
CC
Supply Current per
V
CC
= Max.
V
IN
= 3.4V
(3)
0.5
2.0
mA
Input @ TTL HIGH
I
CCD
Supply Current per
V
CC
= Max.,
V
IN
= V
CC
0.15
0.25
mA/
Input per MHz
(4)
Outputs Open
V
IN
= GND
MHz
OE = GND; LE = Vcc
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply
V
CC
= Max.,
V
IN
= V
CC
1.5
3.5
(5)
mA
Current
(6)
Outputs Open
V
IN
= GND
f
CP
= 10 MH
Z
50% Duty Cycle
V
IN
= 3.4V
1.8
4.5
(5)
OE = GND; LE = Vcc
V
IN
= GND
f
I
= 5 MH
Z
One Bit Toggling
V
CC
= Max.,
V
IN
= V
CC
3.0
6.0
(5)
Outputs Open
V
IN
= GND
f
CP
= 10 MH
Z
50% Duty Cycle
V
IN
= 3.4V
5.0
14.0
(5)
OE = GND; LE = Vcc
V
IN
= GND
Eight Bits Toggling
f
I
= 2.5 MH
Z
50% Duty Cycle
5
PS2025A 03/11/96
PI74FCT841T/843T/845T
(25
(25
(25
(25
(25
S
ERIES
) P174FCT2841T
BUS INTERFACE LATCHES
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PI74FCT841/2841T Switching Characteristics over Operating Range
841AT/2841AT
841BT/2841BT
841CT/2841CT
Com.
Com.
Com.
Parameters
Description
Conditions
(1)
Min
Max
Min
Max
Min
Max
Unit
t
PLH
Propagation Delay
C
L
= 50 pF
1.5
9.0
1.5
6.5
1.5
5.5
ns
t
PHL
D
N
to Y
N
R
L
= 500
(LE = HIGH)
C
L
= 300 pF
(3)
1.5
8.0
1.5
13.0
1.5
13.0
ns
R
L
= 500
t
SU
Setup Time
C
L
= 50 pF
2.5
--
2.5
--
2.5
--
ns
Data to LE
R
L
= 500
t
H
Hold Time
2.5
--
2.5
--
2.5
--
ns
Data to LE
t
PLH
Propagation Delay
C
L
= 50 pF
1.5
12.0
1.5
8.0
1.5
6.4
ns
t
PHL
LE to Y
N
R
L
= 500
C
L
= 300 pF
(3)
--
16.0
--
15.5
--
15.0
ns
R
L
= 500
t
W
LE Pulse Width
(3)
C
L
= 50 pF
4.0
--
4.0
--
4.0
--
ns
(HIGH)
R
L
= 500
t
PZH
Output Enable Time
C
L
= 50 pF
1.5
10.0
1.5
8.0
1.5
6.5
ns
t
PZL
OE to Y
N
R
L
= 500
C
L
= 300 pF
(3)
1.5
23.0
1.5
14.0
1.5
12.0
ns
R
L
= 500
t
PHZ
Output Disable Time
(3)
C
L
= 50 pF
1.5
7.0
1.5
6.0
1.5
5.7
ns
t
PLZ
OE to Y
N
R
L
= 500
C
L
= 5 pF
(3)
1.5
8.0
1.5
7.0
1.5
6.0
ns
R
L
= 500
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
6
PS2025A 03/11/96
PI74FCT841T/843T/845T
(25
(25
(25
(25
(25
S
ERIES
) P174FCT2841T
BUS INTERFACE LATCHES
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PI74FCT843T Switching Characteristics over Operating Range
843AT
843BT
843CT
Com.
Com.
Com.
Parameters
Description
Conditions
(1)
Min
Max
Min
Max
Min
Max
Unit
t
PLH
Propagation Delay
C
L
= 50 pF
1.5
9.0
1.5
6.5
1.5
5.5
ns
t
PHL
D
N
to Y
N
R
L
= 500
(LE = HIGH)
C
L
= 300 pF
(3)
1.5
8.0
1.5
13.0
1.5
13.0
ns
R
L
= 500
t
SU
Setup Time
C
L
= 50 pF
2.5
--
2.5
--
2.5
--
ns
Data to LE
R
L
= 500
t
H
Hold Time
2.5
--
2.5
--
2.5
--
ns
Data to LE
t
PLH
Propagation Delay
C
L
= 50 pF
1.5
12.0
1.5
8.0
1.5
6.4
ns
t
PHL
LE to Y
N
R
L
= 500
C
L
= 300 pF
(3)
1.5
16.0
1.5
15.5
1.5
15.0
ns
R
L
= 500
t
PLH
Propagation Delay
C
L
= 50 pF
1.5
11.0
1.5
8.0
1.5
7.0
ns
PRE to Y
N
R
L
= 500
t
REM
Recovery Time
1.5
11.0
1.5
10.0
1.5
9.0
ns
PRE to Y
N
t
PLH
Propagation Delay
1.5
11.0
1.5
10.0
1.5
9.0
ns
CLR to Y
N
t
REM
Recovery Time
(3)
1.5
13.0
1.5
10.0
1.5
9.0
ns
CLR to Y
N
t
W
LE Pulse Width
(3)
(HIGH)
4.0
--
4.0
--
4.0
--
ns
t
W
PRE Pulse Width
(3)
(LOW)
5.0
--
4.0
--
4.0
--
ns
t
W
CLR Pulse Width
(3)
(LOW)
4.0
--
4.0
--
4.0
--
ns
t
PZH
Output Enable Time
C
L
= 50 pF
1.5
10.0
1.5
8.0
1.5
6.5
ns
t
PZL
OE to Y
N
R
L
= 500
C
L
= 300 pF
(3)
1.5
23.0
1.5
14.0
1.5
12.0
ns
R
L
= 500
t
PHZ
Output Disable Time
(3)
C
L
= 50 pF
1.5
7.0
1.5
6.5
1.5
5.7
ns
t
PLZ
OE to Y
N
R
L
= 500
C
L
= 5 pF
(3)
1.5
8.0
1.5
7.0
1.5
6.0
ns
R
L
= 500
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
7
PS2025A 03/11/96
PI74FCT841T/843T/845T
(25
(25
(25
(25
(25
S
ERIES
) P174FCT2841T
BUS INTERFACE LATCHES
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PI74FCT845T Switching Characteristics over Operating Range
845AT
845BT
845CT
Com.
Com.
Com.
Parameters
Description
Conditions
(1)
Min
Max
Min
Max
Min
Max
Unit
t
PLH
Propagation Delay
C
L
= 50 pF
1.5
9.0
1.5
6.5
1.5
5.5
ns
t
PHL
D
N
to Y
N
R
L
= 500
(LE = HIGH)
C
L
= 300 pF
(3)
1.5
8.0
1.5
13.0
1.5
13.0
ns
R
L
= 500
t
SU
Setup Time
C
L
= 50 pF
2.5
--
2.5
--
2.5
--
ns
Data to LE
R
L
= 500
t
H
Hold Time
2.5
--
2.5
--
2.5
--
ns
Data to LE
t
PLH
Propagation Delay
C
L
= 50 pF
1.5
12.0
1.5
8.0
1.5
6.4
ns
t
PHL
LE to Y
N
R
L
= 500
C
L
= 300 pF
(3)
1.5
16.0
1.5
15.5
1.5
15.0
ns
R
L
= 500
t
PLH
Propagation Delay
C
L
= 50 pF
1.5
11.0
1.5
8.0
1.5
7.0
ns
PRE to Y
N
R
L
= 500
t
REM
Recovery Time
(3)
1.5
11.0
1.5
10.0
1.5
9.0
ns
PRE to Y
N
t
PLH
Propagation Delay
1.5
11.0
1.5
10.0
1.5
9.0
ns
CLR to Y
N
t
REM
Recovery Time
(3)
1.5
13.0
1.5
10.0
1.5
9.0
ns
CLR to Y
N
t
W
LE Pulse Width
(3)
(HIGH)
4.0
--
4.0
--
4.0
--
ns
t
W
PRE Pulse Width
(3)
(LOW)
5.0
--
4.0
--
4.0
--
ns
t
W
CLR Pulse Width
(3)
(LOW)
4.0
--
4.0
--
4.0
--
ns
t
PZH
Output Enable Time
C
L
= 50 pF
1.5
10.0
1.5
8.0
1.5
6.5
ns
t
PZL
OE to Y
N
R
L
= 500
C
L
= 300 pF
(3)
1.5
23.0
1.5
14.0
1.5
12.0
ns
R
L
= 500
t
PHZ
Output Disable Time
(3)
C
L
= 50 pF
1.5
7.0
1.5
6.5
1.5
5.7
ns
t
PLZ
OE to Y
N
R
L
= 500
C
L
= 5 pF
(3)
1.5
8.0
1.5
7.0
1.5
6.0
ns
R
L
= 500
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
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