1
PS8667A 10/04/04
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LVDS High-Speed Differential
Line Receivers
Features
Signaling Rates >400Mbps (200 MHz)
Single 3.3V Power Supply Design
Accepts 350mV (typical) Differential Swing
Maximum Differential Skew of 0.35ns
Integrated 110-Ohm termination on PI90LVTxxxx
Maximum Propagation Delay of 4.7ns
Low Voltage TTL (LVTTL) Outputs
Industrial Temperature Operating Range: -40C to 85C
Open, Short, and Terminated Fail Safe
Meets or Exceeds ANSI/TIA/EIA-644 LVDS Standard
Packaging (Pb-free & Green available):
-16-Pin TSSOP (L )
-16-Pin SOIC (W)
-8-Pin SOIC (W)
-8-Pin MSOP (U)
PI90LV/LVT3486
PI90LV/LVT9637
PI90LV3486/PI90LVT3486
PI90LV9637/PI90LVT9637
Description
The PI90LV/LVT3486 and PI90LV/LVT9637 are differential line
receivers that use low-voltage differential signaling (LVDS) to
support data rates in excess of 400 Mbps. These products are
designed for applications requiring high-speed, low-power con-
sumption and low noise generation.
A differential input signal (350mV) is translated by the device to 3V
CMOS output level.
Applications
Applications include point-to-point and multidrop baseband data
transmission over controlled impedance media of approximately
100-ohms. The transmission media can be printed circuit board
traces, backplanes, or cables.
The PI90LV/LVT3486 and PI90LV/LVT9637, as well as companion
line drivers PI90LV/LVB3487 and PI90LV/LVB9638 provide new
alternatives to RS-232, PECL, and ECL devices for high-speed,
point-to-point interface applications.
16-Pin
W, L
8-Pin
W,U
2
PS8667A 10/04/04
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PI90LV3486/PI90LVT3486
PI90LV9637/PI90LVT9637
LVDS High-Speed Differential Line Receivers
Function Tables
Pin Descriptions
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PI90LV/LVT9637
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Supply Voltage (V
CC
) ....................................... 0.3V to +4.0V
Input Voltage (R
IN+
, R
IN-
) ............................... 0.3V to +3.9V
Enable Input Voltage (EN) ...................... 0.3V to (V
CC
+0.3V)
Output Voltage (R
OUT
) .......................... 0.3V to (V
CC
+0.3V)
S Package .................................................................... 750mW
Derate S Package ................................8.2mW/C above +25C
Storage Temperature Range .......................... 65C to +150C
Lead Temperature Range Soldering (4s) ...................... +260C
Maximum Junction Temperature .................................. +150C
ESD Rating ...................................................................
10kV
Note:
Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Absolute Maximum Ratings
(see Note 1, Page 4)
Recommended Operating Conditions
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3
PS8667A 10/04/04
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PI90LV3486/PI90LVT3486
PI90LV9637/PI90LVT9637
LVDS High-Speed Differential Line Receivers
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1
Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 2)
4
PS8667A 10/04/04
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PI90LV3486/PI90LVT3486
PI90LV9637/PI90LVT9637
LVDS High-Speed Differential Line Receivers
Switching Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 3,4,7,8)
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Notes:
1.
"Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation.
2.
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless
otherwise specified.
3.
All typicals are given for: V
CC
= +3.3V, T
A
= +25C.
4.
Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50
,
t
R
and t
F
(0% to 100%)
3
ns for R
IN
.
5.
The VCMR range is reduced for larger V
ID
. Example : if V
ID
= 400mV, the VCMR is 0.2V to 2.2V. The fail-safe condition with inputs
shorted is valid over a common-mode range of 0V to 2.3V. A V
ID
up tp V
CC
- 0V may be applied to the R
IN+
/ R
IN-
inputs with the
Common-Mode voltage set to V
CC
/2. Propagation delay and Differential Pulse skew decrease when VID is increased from 200mV to
400mV. Skew specifications apply for 200mV
V
ID
800mV over the common mode range.
6.
tskd1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
same channel.
7.
t
SKD2
, Channel-to-Channel Skew, is defined as the difference between the propagation delay of one channel and that of the others on the
same chip with any event on the inputs.
8.
t
SKD3
, Part-to-Part Skew, is the differential Channel-to-Channel skew of any event between devices. This specification applies to devices
at the same V
CC
,and within 5C of each other within the operating temperature range.
9.
t
SKD4
, Part-to-Part Skew, is the differential Channel-to-Channel skew of any event between devices. This specification applies
to devices over recommended operating temperature and voltage ranges, and across process distribution. tskd4 is defined as IMax - Mini
differential propagation delay.
10. Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at
a time, do not exceed maximum junction temperature specification.
11. C
L
includes probe and jig capacitance.
12. V
CC
is always higher than R
IN+
and R
IN-
voltage. R
IN-
and R
IN+
are allowed to have a voltage range -0.2V to V
CC
- V
ID
/2.
However, to be compliant with AC specifications, the common voltage range 0.1V to 2.3V.
13. fmax generator input conditions: t
R
= t
F
< 1ns, (0% to 100%), 50% duty cycle, differential (1.05V to1.35V peak to peak).
Output Criteria: duty cycle = 60%/40%, V
OL
(max 0.4V), V
OH
(min 2.7V), Load = 10pF (stray plus probes).
5
PS8667A 10/04/04
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PI90LV3486/PI90LVT3486
PI90LV9637/PI90LVT9637
LVDS High-Speed Differential Line Receivers
EN
Generator
R
OUT
R
L
R
IN+
R
IN
50
C
L
S
1
V
CC
Device
Under
Test
Parameter Measurement Information
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
Generator
Receiver Enabled
RIN+
ROUT
R
RIN
CL
50
50
t
TLH
20%
R
OUT
V
ID =
200mV
R
IN-
R
IN+
V
OL
t
PHLD
t
PLHD
+1.3V
+1.1V
1.5V
0V (Differential)
+1.2V
1.5V
80%
80%
20%
t
THL
Figure 3. Receiver Three-State Delay Test Circuit
C
L
includes load and test jig capacitance.
S
1
= V
CC
for T
PZL
, and T
PLZ
measurements
S
1
= GND for t
PZH
and t
PHZ
measurements
6
PS8667A 10/04/04
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PI90LV3486/PI90LVT3486
PI90LV9637/PI90LVT9637
LVDS High-Speed Differential Line Receivers
Figure 4. Receiver Three-State Delay Waveforms
Output When
V
ID
= +100mV
Output When
V
ID
= -100mV
EN* When EN = GND
EN When EN* = V
CC
3V
0V
0.5V
0.5V
50%
50%
1.5V
1.5V
1.5V
1.5V
t
PZL
t
PZH
V
CC
GND
t
PLZ
t
PHZ
0V
3V
V
OH
V
OL
Figure 5. Point-to-Point Application
ANY LVDS DRIVER
Enable
Data
Input
1/4 PI90LV3486
Data
Output
RT
+
100
Balanced System
7
PS8667A 10/04/04
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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI90LV3486/PI90LVT3486
PI90LV9637/PI90LVT9637
LVDS High-Speed Differential Line Receivers
Packaging Mechanical: 16-Pin MSOP (U)
.0040
.0098
SEATING PLANE
.013
.020
.050
BSC
.016
.0075
.0098
1
8
.0099
.0196
0-8
.050
.149
.157
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
3.78
3.99
.189
.196
4.80
5.00
1.27
.016
.026
1.35
1.75
.2284
.2440
5.80
6.20
0.406
0.660
0.330
0.508
0.10
0.25
0.40
1.27
0.19
0.25
0.25
0.50
x 45
.053
.068
REF
Packaging Mechanical: 8-Pin SOIC (W)
15
MAX
15
MAX
Detail A
Detail A
.112
.120
2.85
3.05
.114
.122
2.90
3.10
.114
.122
2.90
3.10
.010
0
- 6
15 Max.
15 Max.
0.25
Gauge
Plane
.003
.012
.016
.028
.037
0.40
0.70
0.95
REF
0.07
0.30
.003
.012
0.07
0.30
8
PS8667A 10/04/04
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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI90LV3486/PI90LVT3486
PI90LV9637/PI90LVT9637
LVDS High-Speed Differential Line Receivers
Packaging Mechanical: 16-Pin TSSOP (L)
.193
.201
.047
max.
.002
.006
SEATING
PLANE
.0256
BSC
.018
.030
.004
.008
.252
BSC
1
16
.169
.177
X.XX
X.XX
DENOTES CONTROLLING
DIMENSIONS IN MILLIMETERS
0.05
0.15
6.4
0.45
0.75
0.09
0.20
4.3
4.5
1.20
4.9
5.1
0.65
0.19
0.30
.007
.012
SEATING PLANE
.050
BSC
1
16
0-8
.149
.157
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
3.78
3.99
.386
.393
9.80
10.00
1.27
.053
.068
1.35
1.75
.2284
.2440
5.80
6.20
.0040
.0098
0.10
0.25
.013
.020
.0155
.0260
0.330
0.508
0.393
0.660
.0075
.0098
0.25
0.50
.0099
.0196
x 45
0.19
0.25
.016
.050
0.41
1.27
REF
Packaging Mechanical: 16-Pin SOIC (W)
9
PS8667A 10/04/04
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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI90LV3486/PI90LVT3486
PI90LV9637/PI90LVT9637
LVDS High-Speed Differential Line Receivers
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
Ordering Information
Ordering Code
Package Code
Package Type
PI90LV3486L
L
16-pin TSSOP
PI90LV3486LE
L
Pb-free & Green, 16-pin TSSOP
PI90LV3486W
W
16-pin SOIC
PI90LV3486WE
W
Pb-free & Green, 16-pin SOIC
PI90LVT3486L
L
16-pin TSSOP
PI90LVT3486LE
L
Pb-free & Green, 16-pin TSSOP
PI90LVT3486W
W
16-pin SOIC
PI90LVT3486WE
W
Pb-free & Green, 16-pin SOIC
PI90LV9637U
U
8-pin MSOP
PI90LV9637UE
U
Pb-free & Green, 8-pin MSOP
PI90LV9637W
W
8-pin SOIC
PI90LV9637WE
W
Pb-free & Green, 8-pin SOIC
PI90LVT9637U
U
8-pin MSOP
PI90LVT9637UE
U
Pb-free & Green, 8-pin MSOP
PI90LVT9637W
W
8-pin SOIC
PI90LVT9637WE
W
Pb-free & Green, 8-pin SOIC
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