1
PS8536A 05/21/01
Features
Master/Slave clock selection in a backplane application
160 MHz operation (typical)
100ps duty cycle distortion (typical)
50ps channel to channel skew (typical)
3.3V power supply design
Glitch-free power on at CLKI/O pins
Low Power design (16mA @ 3.3V static)
Accepts small swing (300mV typical) differential signal levels
Industrial temperature operating range (40C to +85C)
Available in 24-pin TSSOP Packaging (L)
General Description
PI90LVB16 is a six-channel LVTTL clock distribution driver with 50
picosecond channel-to-channel skew. It translates one BLVDS
(Bus Low-Voltage Differential Signaling) input signal into six LVTTL-
compatible output signals for distribution to adjacent chips on the
same board. The PI90LVB16 accepts BLVDS (300mV typical) differ-
ential input levels, and translates them to 3V CMOS output levels.
The 160MHz PI90LVB16 can be the master clock, driving inputs of
other clock I/O pins in a multipoint environment. It can also drive
the BLVDS backplane with a separate channel acting as a return/
source LVTTL clock source. The master/slave clock selection of the
driving source is controlled by the CrdCLK
IN
and the DE pins. An
output enable pin OE, when high, forces all CLK
OUT
pins high.
A backplane clock distribution network must be able to drive many
transmission line stubs. The Bus LVDS feature of the PI90LVB16 is
ideal for driving data transfers in large, high-performance backplane
system applications. The device can be used as a source synchro-
nous driver to distribute clock signals within data and telecommu-
nications systems.
Function Diagram
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PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
Delay
MUX
CLK
OUT0
CLK
OUT1
CLK
OUT5
CrdCLK
IN
D
R
DE
OE
CLKI/0
CLKI/0+
Receive Mode Truth Table
t
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V
V
7
0
.
0
L
L = Low Logic State; H = High Logic State; X = Irrelevant
Z = High Impedance
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Driver Mode Truth Table
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2
PS8536A 05/21/01
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
GND
OE
NC
V
CCA
GNDA
CLKI/0+
CLKI/0
GNDA
CrdCLK
IN
NC
DE
GND
V
CC
CLK
OUT0
GND
CLK
OUT1
V
CC
CLK
OUT2
GND
CLK
OUT3
V
CC
CLK
OUT4
GND
CLK
OUT5
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Connection Diagram
TSSOP Package Pin Description
24-Pin
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PS8536A 05/21/01
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PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
Supply Voltage Range, V
CC .....................................................................................
0.3V to +4V
Enable Input Voltage (DE, OE, CrdCLK
IN
) .............................................. 0.3V to +4V
Voltage (CLK
OUT
)
............................................................... 0.3V to (V
CC
+ 0.3V)
Voltage (CLKI/O)
............................................................... 0.3V to (V
CC
+ 0.3V)
Driver Short Circuit Current ....................................................................... momentary
Receiver Short Circuit Current .................................................................. momentary
Maximum Package Power Dissipation at +25C
TSSOP Package
................................................................................... 1500mW
Derate TSSOP Package ..................................................... 8.2mW/C above +25C
JA ...........................................................................................................................................
95C/W
JC ...........................................................................................................................................
30C/W
Storage Temperature Range .............................................................65C to +150C
Lead Temperature Range (Soldering, 4s) ........................................................... 260C
ESD Ratings: HBM
(2) ..................................................................................................................
9kV
CLK
OUT(05) ..........................................................................................................................
2kV
CDM
(2) ..................................................................................................................................
>1000V
Machine Model
(2) ...............................................................................................................
>200V
Absolute Maximum Ratings
(1)
Recommended Operating Conditions
Min.
Typ.
Max
Units
Supply Voltage (V
CC)
+3.0
+3.3
+3.6
V
CrdCLK
IN
, DE, OE Input Voltage
0
V
CC
V
Operating Free Air Temperature (T
A
) 40
24
+85
C
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4
PS8536A 05/21/01
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specificed
(3,4)
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PS8536A 05/21/01
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PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
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A
DC Electrical Characteristics
(continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specifice
d
(3,4)
Switching Characteristics
Differential Receiver Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specificed
(7,8)
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6
PS8536A 05/21/01
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
Switching Characteristics
Differential Driver Timing Requuirements
(Over supply voltage and operating temperature ranges, unless otherwise specificed
(7,8)
Notes:
1. Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. These ratings
are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics specifies conditions of
device operation.
2. ESD Rating: ESD qualification is performed per the following: HBM (1.5k
, 100pF), Machine Model (250V, 0
), IEC 1000-4-2. All V
CC
pins connected together, all ground pins connected together.
3. Current into device pins are defined as positive. Current out of device pins defined as negative. All voltages are referenced to ground except
VID, VOD, VTH, and VTL
4. All typicals are given for: V
CC
= +3.3V and T
A
= +25C.
5. The VCMR range is reduced for larger VID. Example: If VID=400 mV, then VCMR is 02V to 2.2VAVID up to
V
CC
-0V
may be applied
between the CLKI/O+ and CLKI/O inputs, with the Common Mode set to V
CC
/2.
6. Only one output should be momentarily shorted at a time. Do not exceed package power dissipation rating.
7. C
L
includes probe and fixture capacitance.
8. Generator waveform for all tests unless otherwise specified: f = 25 MHz, Zo = 50
, t
r
= 1ns, t
f
= 1ns (10%90%). To ensure fastest
propagation delay and minimum skew, clock input edge rates should not be slower than 1ns/V; control signals not slower than 3ns/V.
In general, the faster the input edge rate, the better the AC performance,
9. All device output transition times are based on characterization measurements and are guaranteed by design.
10. t
SKIR
is the difference in receiver propagation delay
t
PLH
-t
PHL
of one device, and is the duty cycle distortion of the output at any given
temperature and V
CC
. The propagation delay specification is a device-to-device worst case over process, voltage and temperature.
11. t
SK2R
is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction.
This parameter is guaranteed by design and characterization.
12. t
SK3R
part-to-part skew, is the difference in receiver propagation delay between devices of any outputs switching in the same direction.
This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. t
SK3R
is
defined as Max-Min differential propagation delay. This parameter is guaranteed by design and characterization.
13. t
SK1D
is the difference in driver propagation delay
t
PLH
-t
PHL
and is the duty cycle distortion of the CLKI/O outputs.
14. t
SK2D
part-to-part skew, is the difference in driver propagation delay between devices of any outputs switching in the same direction. This
specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. t
SK2D
is
defined as Max-Min differential propagation delay.
15. Generator input conditions: t
r
t
f
< 1ns, 50% duty cycle, differential (1.10V to 1.35V pk-pk). Output Criteria: 60%/40% duty cycle,
V
OL
(max) 0.4V, V
OH
(min) 2.7V, Load - 7pF (stray plus probes).
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1
0
6
1
z
H
M
7
PS8536A 05/21/01
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PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
Parameter Measurement Information
V
ID
= 250mV
V
OH
V
OL
t
PLHDR
t
TLHR
V
CC
/2
V
CC
/2
t
THLR
t
PHLDR
CLKI/0
CLKI/0+
CLK
OUT
+1.35V
80%
80%
20%
20%
+1.10V
Generator waveform for all test unless otherwise specificed: f = 25MHz, 50% Duty Cycle, Z0 = 50
9
, t
THL
= 1ns
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
C
L
50
9
CLK
OUT
CLKI/0+
CLKI/0
Generator
D.U.T.
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8
PS8536A 05/21/01
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
Figure 3. Output Enable (OE) Test Circuit
Figure 4. Output Enable (OE) Delay Waveforms
OE
tPLHOER
tPHLOER
50%
S1 = 0.95V
S1+ = 1.2V
50%
50%
50%
CLK
OUT
S1 = 0.95V
S1+ = 1.2V
CLK
OUT
V
OH
V
OL
V
OH
V
CC
0V
Parameter Measurement Information
OE
0.95V
0.95V
1.2V
+
Generator
50
9
CL
Test
Point
Test
Point
CLKOUT
9
PS8536A 05/21/01
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PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
CrdCLK
IN
DE
D
CL
CL
RL
Figure 6. Driver Propagation Delay Test Circuit
2V
0.8V
DE
D
R
L
/2 = 18.75
9
R
L
/2 = 18.75
9
VOS
VOD
Figure 5. Differential Driver DC Test
Parameter Measurement Information
Figure 7. Driver Propagation Delay and Transition Time Waveforms
t
PLHCrd
0 Differential
0 Differential
t
THLDD
t
PHLDR
CrdCLK
IN
CLKI/0
CLKI/0+
V
DIFF= [CLKI/)+] [CLKI/)]
V
CC
V
OH
V
OL
80%
50%
80%
20%
20%
0V
t
PHLCrd
t
TLHDD
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10
PS8536A 05/21/01
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
Figure 8. CrdCLK
IN
Propagation Delay Time Test Circuit
tPLHCrd
50%
50%
50%
50%
CLK
OUT
CLK
IN
tPHLCrd
V
OL
V
OH
V
CC
0V
Figure 9. CrdCLK
IN
Propagation Delay Time Waveforms
Parameter Measurement Information
C
L
50
9
CLK
OUT
CrdCLK
IN
Generator
D.U.T.
11
PS8536A 05/21/01
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PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
Figure 10. Driver 3-State Test Circuit
CrdCLK
IN
V
CC
Pulse
Generator
DE
0V
D
CL
CL
RL/2
1.2V
RL/2
50
9
1.2V
DE
0V
V
CC
V
OL
V
OH
CLKI/O+ (CrdCLK
IN
- L)
CLKI/O (CrdCLK
IN
- H)
CLKI/O+ (CrdCLK
IN
-H)
CLKI/O (CrdCLK
IN
- L)
1.2V
50%
50%
50%
50%
50%
t
PLZD
t
PZLD
t
PZhD
t
PHZD
Figure 11. Driver 3-State Waveforms
Parameter Measurement Information
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12
PS8536A 05/21/01
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
24-Pin TSSOP (L) Package
Ordering Information
e
d
o
C
g
n
i
r
e
d
r
O
e
m
a
N
e
g
a
k
c
a
P
e
p
y
T
e
g
a
k
c
a
P
e
g
n
a
R
g
n
it
a
r
e
p
O
L
6
1
B
V
L
0
9
I
P
4
2
L
P
O
S
S
T
n
i
p
-
4
2
C
5
8
o
t
C
0
4
.303
.311
.047
1.20
.002
.006
SEATING
PLANE
.0256
BSC
.018
.030
.004
.008
.252
BSC
1
24
.169
.177
X.XX
X.XX
DENOTES CONTROLLING
DIMENSIONS IN MILLIMETERS
0.05
0.15
6.4
0.45
0.75
0.09
0.20
4.3
4.5
7.7
7.9
0.65
0.19
0.30
.007
.012
Max
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