1
PS8187A 06/29/99
Low On-Resistance (33
typ) Minimizes Distortion and
Error Voltages
Low Glitching Reduces Step Errors in Sample-and-Holds.
Charge Injection, 2pC typ
Single-Supply Operation (+2.5V to +16V)
Improved Second Sources for MAX4501/MAX4502
On-Resistance Matching Between Channels, <2
On-Resistance Flatness, <6
max
Low Off-Channel Leakage, <5nA @ +85oC
TTL/CMOS Logic Compatible
Fast Switching Speed, tON < 150ns
Guaranteed Break-Before-Make action (PS303 only)
eliminates momentary crosstalk
Rail-to-Rail Analog Signal Dynamic Range
Low Power Consumption, <5
W
MSOP Package minimizes board area
Applications
Audio, Video Switching and Routing
Portable Instruments
Data Acquisition Systems
Sample-and-Holds
Telecommunication Systems
Battery-Powered Systems
Description
The PS301/PS302/PS303 are improved high precision, medium
voltage analog switches designed to operate with single power
supplies. The PS301 is a single-pole single-throw (SPST), nor-
mally open (NO) switch. The PS302 has the same pinout as the
PS301 but is a normally closed (NC) switch. The PS303 has one
normally open (NO) and one normally closed (NC) switch per
package. Each switch conducts current equally well in either
direction when on. In the off state each switch blocks voltages up
to the power-supply rail.
With a +5V power supply, the PS301/PS302/PS303 guarantee
<60
ON-resistance
.
ON-resistance matching between channels
is within 2
. ON-resistance flatness is less than
6
over the
specified range. All three devices guarantee low leakage currents
(<100pA @ 25oC, <10nA @ +85oC) and fast switching speeds
(tON < 150ns). Break-before-make switching action protects
against momentary crosstalk (PS303).
For single-supply operation below 5V, the PI5A317/318/319
are also recommended.
1
0
3
S
P
c
i
g
o
L
h
c
ti
w
S
0
1
F
F
O
N
O
Switches shown for logic "0" input
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PS301/PS302/PS303
Functional Diagrams, Pin Configurations, and Truth Tables
Top Views
Features
For free samples and the latest literature: www.pericom.com, or phone 1-800-435-2336
6
7
8
5
1
2
3
4
COM
N.C.
N.C.
V+
NC
IN
N.C.
GND
PS302
6
7
8
5
1
2
3
4
COM
N.C.
N.C.
V+
NO
IN
N.C.
GND
PS301
2
0
3
S
P
c
i
g
o
L
h
c
ti
w
S
0
1
N
O
F
F
O
6
7
8
5
1
2
3
4
NO
COM
NC
GND
V+
N.C.
N.C.
IN
PS303
3
0
3
S
P
c
i
g
o
L
C
N
O
N
0
1
N
O
F
F
O
F
F
O
N
O
Precision, Single-Supply
SPST Analog Switches
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2
PS8187A 06/29/99
PS301/PS302/PS303
Precision, Single Supply SPST Analog Switches
Absolute Maximum Ratings
Caution: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied.
Thermal Information
Continuous Power Dissipation
Plastic DIP (derate 6mW/
C above +70
C) . . . . . . . . . 500mW
Narrow SO (derate 6mW/
C above +70
C) . . . . . . . . 450mW
MSOP (derate 4mW/
C above +70
C) . . . . . . . . . . . . 330mW
Storage Temperature . . . . . . . . . . . . . . . . . . -65
C to +150
C
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . +300
C
Note 1: Signals on NC, NO, COM, or IN exceeding V+ or
GND are clamped by internal diodes. Limit forward diode
current to 30mA maximum.
Voltages Referenced to GND
V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +17V
V
IN
, V
COM
, V
NC
, V
NO
(Note 1) . . . . . . . . . -2V to (V+) +2V
or 30mA, whichever occurs first
Current (any terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, COM, NO, NC
(pulsed at 1ms, 10% duty cycle) . . . . . . . . . . . . . . . . . . 100mA
ESD per Method 3015.7 . . . . . . . . . . . . . . . . . . . . . . . >2000V
Electrical Specifications - Single +5V Supply
(V+ = 5V +10%, GND = 0V, V
INH
= 2.4V, V
INL
= 0.8V)
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.
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+
=
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V
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+
=
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C
=
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=
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1
5
2
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F
,
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5
=
+
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V
,
A
m
1
=
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V
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N
,
V
3
,
V
2
,
V
1
=
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2
2
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C
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V
,
V
5
.
5
=
+
V
M
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C
,
V
1
=
V
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N
V
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N
V
5
.
4
=
5
2
1
.
0
1
0
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0
1
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0
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5
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V
M
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V
,
V
5
.
4
=
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0
1
0
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0
1
.
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5
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,
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=
V
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N
V
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C
N
V
5
=
5
2
2
.
0
4
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0
2
.
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0
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3
PS8187A 06/29/99
PS301/PS302/PS303
Precision, Single Supply SPST Analog Switches
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it
is
o
P
+
I
V
,
V
5
.
5
=
+
V
N
I
,
+
V
r
o
V
0
=
ff
o
r
o
n
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sl
e
n
n
a
h
c
ll
a
1
1
A
Electrical Specifications - Single +5V Supply
(continued)
(V + = 5V 10%, GND = 0V, V
INH
=2.4V, V
INL
= 0.8V)
Notes:
1. The algebraic convention, where the most negative value is a minimum and the most positive is a maximum, is used in
this data sheet.
2. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing.
3. Guaranteed by design
4.
R
=
R
max.
- R
min.
5. Flatness is defined as the difference between the maximum and minimum value of on-resistance measured.
6. Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at +25C.
7. Off Isolation = 20log
10
[V
COM
/ (V
NC
or V
NO
)]. See Figure 5.
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4
PS8187A 06/29/99
PS301/PS302/PS303
Precision, Single Supply SPST Analog Switches
Electrical Specifications - Single +12V Supply
(V+ = 12V 10%, GND = 0V, V
INH
= 5V, V
INL
= 0)
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,
V
2
1
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A
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1
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V
6
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1
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F
1
1
0
.
0
1
A
Electrical Specifications - Single +3.3V Supply
(V+ = 3.3V 10%, GND = 0V, V
INH
= 2.4V, V
INL
= 0.8V)
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Q
C
L
V
,
F
n
1
=
N
E
G
,
V
0
=
R
N
E
G
=
0
4
e
r
u
gi
F
,
5
2
1
5
C
p
y
l
p
p
u
S
t
n
e
rr
u
C
yl
p
p
u
S
e
vi
ti
s
o
P
+
I
=
+
V
3.6 V
,
V
N
I
,
+
V
r
o
V
0
=
ff
o
r
o
n
o
sl
e
n
n
a
h
c
ll
a
ll
u
F
1
1
0
.
0
1
A
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5
PS8187A 06/29/99
PS301/PS302/PS303
Precision, Single Supply SPST Analog Switches
Test Circuits/Timing Diagrams
Figure 2. Switching Time
Figure 3. Break-Before-Make Interval (PS303 only)
Figure 4. Charge Injection
GND
+5V
NO
or NC
COM
V
COM = 3V
Logic
Input
IN
V+
tr <20ns
tf <20ns
V
OUT
= V
COM
R
L
R
L +
R
ON
(
)
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE
V
OUT
R
L
1k
C
L
35pF
LOGIC INPUT WAVEFORMS INVERTED FOR
SWITCHES THAT HAVE OPPOSITE LOGIC
t
OFF
t
ON
V
OUT
90%
Logic
Input
Switch
Output
+3V
0V
0V
50%
90%
V+
NO1
GND
NC
NO
+3V
IN
V+
+3V
50%
90%
90%
Logic
Input
Logic
Input
C
L
0V
0V
Switch
Output
V
OUT
INCLUDES FIXTURE AND STRAY CAPACITANCE.
tD
V
C
L
R
L
35
OUT
300
pF
V+
+5V
NO or
NC
GND
COM
R
GEN
V
OUT
C
L
1nF
V
OUT
V
OUT
IN
V
GEN
ON
ON
OFF
OFF
OFF
OFF
IN
Q = (
V
OUT
)(C
L
)
IN
Logic
Input
IN POLARITY DEPENDS ON NO OR NC SWITCH FUNCTION
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6
PS8187A 06/29/99
PS301/PS302/PS303
Precision, Single Supply SPST Analog Switches
Test Circuits/Timing Diagrams (continued)
Figure 5. Off Isolation
Figure 7. Channel-Off Capacitance
Figure 6. Crosstalk
Figure 8. Channel-On Capacitance
V+
+5V
NC
Capacitance
Meter
or NO
COM
GND
10nF
IN
0V or
2.4V
f = 1kHz
V+
+5V
NC
Analyzer
GND
or NO
COM
10nF
IN
0V or
2.4V
COM
R
L
V+
+5V
Analyzer
N02
GND
COM1
10nF
IN2
R
L
COM
Signal
Generator 0dBm
0V or
3.5V
0V or
2.4V
COM2
IN1
N01
NC
50
50
V+
+5V
NC
Capacitance
Meter
GND
or NO
COM
10nF
IN
0V or
2.4V
f = 1kHz
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7
PS8187A 06/29/99
PS301/PS302/PS303
Precision, Single Supply SPST Analog Switches
Overvoltage
Proper power-supply sequencing is recommended for all CMOS
devices. Do not exceed the absolute maximum ratings, because
stresses beyond the listed ratings may cause permanent damage to
the devices. Always sequence V+ on first, and then logic inputs.
If power-supply sequencing is not possible, add two small signal
diodes or two current limiting resistors in series with the supply
pins for overvoltage protection (Figure 1). Adding diodes reduces
the analog signal range, but low switch resistance and low leakage
characteristics are unaffected.
Applications Information
Figure 1. Overvoltage protection is accomplished by using two
external blocking diodes or two current limiting resistors.
V+
Positive Supply
COM
NO
Vg
V-
Protection
GND
When powered from +5V the PS301/PS302/PS303 can be oper-
ated with either TTL- or CMOS-Logic levels. If V+ is different
than +5V, the logic threshold level will vary.
Power consumption is minimal when the logic control voltages
reach V+ or GND.
Logic Levels
Ordering Information
t
r
a
P
e
g
n
a
R
.
p
m
e
T
e
g
a
k
c
a
P
3
S
P
1
0
A
P
C
C
0
7
+
o
t
C
0
P
I
D
c
it
s
a
l
P
8
3
S
P
1
0
A
S
C
C
0
7
+
o
t
C
0
O
S
w
o
r
r
a
N
8
3
S
P
1
0 CUA
C
0
7
+
o
t
C
0
P
O
S
M
8
3
S
P
1
0
A
P
E
C
5
8
+
o
t
C
0
4
P
I
D
c
it
s
a
l
P
8
3
S
P
1
0
A
S
E
C
5
8
+
o
t
C
0
4
O
S
w
o
r
r
a
N
8
3
S
P
2
0
A
P
C
C
0
7
+
o
t
C
0
P
I
D
c
it
s
a
l
P
8
3
S
P
2
0
A
S
C
C
0
7
+
o
t
C
0
O
S
w
o
r
r
a
N
8
3
S
P
2
0 CUA
C
0
7
+
o
t
C
0
P
O
S
M
8
t
r
a
P
e
g
n
a
R
.
p
m
e
T
e
g
a
k
c
a
P
A
P
E
2
0
3
S
P
C
5
8
+
o
t
C
0
4
P
I
D
c
it
s
a
l
P
8
A
S
E
2
0
3
S
P
C
5
8
+
o
t
C
0
4
O
S
w
o
r
r
a
N
8
A
P
C
3
0
3
S
P
C
0
7
+
o
t
C
0
P
I
D
c
it
s
a
l
P
8
A
S
C
3
0
3
S
P
C
0
7
+
o
t
C
0
O
S
w
o
r
r
a
N
8
A
U
C
3
0
3
S
P
C
0
7
+
o
t
C
0
P
O
S
M
8
0
3
S
P
3
A
P
E
C
5
8
+
o
t
C
0
4
P
I
D
c
it
s
a
l
P
8
A
S
E
3
0
3
S
P
C
5
8
+
o
t
C
0
4
O
S
w
o
r
r
a
N
8
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
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