1
PS8461 02/16/00
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PS4051/PS4052/PS4053
17V CMOS Analog Multiplexers/Switches
Features
Low On-resistance: 60
typ, with 5V Supplies,
Minimizes Distortion
On-Resistance Matching between channels better than 6
Guaranteed Low Leakage Currents: <0.1nA at +25
o
C
Rail-to-Rail Analog Signal Range
Low Distortion: <0.04% (600
)
Low Crosstalk: 90dB @100kHz
TTL/CMOS Compatible (with +5V or 5V Supplies)
Low Power Consumption.
16-pin Narrow SOIC and QSOP Packages save board area
Pin-compatible upgrades for 74HC4051/4052/4053
Applications
Audio and Video Switching and Routing
Lab and Medical Instrumentation
Low-Voltage Data-Acquisition and Process
Control Systems
Battery-Powered Communication Systems
Description
The PS4051/PS4052/PS4053 are precision low-voltage CMOS
analog multiplexers/switches.
The PS4051 is an eight-channel single-ended mux designed to
select one of eight inputs to a common output. What input is
selected depends on the status of three address bits (ADDA-ADDC).
The PS4052 is a differential four-channel mux, controlled by two
address bits: ADDA, and ADDB. The PS4053 is a triple 2-to-1
mux (or triple SPDT, single-pole double-throw, switch).
The INH (inhibit) pin can be driven high, to open all switches
regardless of address bit status. All control inputs are TTL
compatible when V+ = +5V.
These devices are designed to operate with power supplies
from 2.7V to 8V. Single-supply operation is possible from
+2.7V to +16V.
When on, each switch conducts current equally well in either
direction and can handle rail-to-rail analog signals. In the
off -state each switch blocks voltages up to the power-supply rails.
Off-leakage current is guaranteed to be less than 0.1nA at +25
o
C,
and < 2.5nA at +85
o
C.
These devices are available in 16-pin DIP, Narrow SOIC, and QSOP
packages for operation over the 40
o
C to +85
o
C temperature range.
Functional Block Diagrams and Pin Configurations
Top Views
For free samples and the latest literature: www.pericom.com, or phone 1-800-435-2336
10
11
12
13
14
15
16
9
7
6
5
4
3
2
1
8
NO1
NO3
COM
NO7
INH
NO5
V-
GND
V+
NO2
NO4
NO0
ADDC
NO6
ADDB
ADDA
LOGIC
10
11
12
13
14
15
16
9
7
6
5
4
3
2
1
8
NO0B
NO1B
COMB
NO3B
INH
NO2B
V-
GND
V+
NO1A
NO2A
COMA
NO3A
NO0A
ADDB
ADDA
LOGIC
10
11
12
13
14
15
16
9
7
6
5
4
3
2
1
8
N0B
NCB
NOA
COMA
INH
NCA
V-
GND
V+
COMB
COMC
NOC
ADDC
NCC
ADDB
ADDA
LOGIC
PS4051
PS4052
PS4053
2
PS8461 02/16/00
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PS4051/PS4052/PS4053
17V CMOS Analog Multiplexers/Switches
Caution: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied.
Thermal Information
Continuous Power Dissipation
Plastic DIP (derate 10.5mW/
C above +70
C) .............. 800mW
Narrow SO and QSOP
(derate 8.7mW/
C above +70
C) .................................... 650mW
Storage Temperature ........................................ -65
C to +150
C
Lead Temperature (soldering, 10s) ................................. +300
C
Note 1:
Signals on NO, COM, or logic inputs exceeding V+ or V are
clamped by internal diodes. Limit forward diode current to 30mA.
Absolute Maximum Ratings
Voltages Referenced to V
V+ ..................................................................... 0.3V to + 17V
GND ................................................................. 0.3V to + 17V
GND ......................................................... -0.3V to (V+) + 0.3V
V
IN
, V
COM
, V
NO
(1) ..........................................
(V-) 2V to (V+) + 2V
or 30mA, whichever occurs first
Current (any terminal ) ..................................................... 30mA
Peak Current, COM, NO, NC
(pulsed at 1ms, 10% duty cycle) ..................................... 100mA
ESD per method 3015.7 ............................................... >2000V
1
5
0
4
S
P
H
N
I
C
D
D
A
B
D
D
A
A
D
D
A
h
c
t
i
w
S
n
O
1
X
X
X
e
n
o
N
0
0
0
0
0
O
N
0
0
0
1
1
O
N
0
0
1
0
2
O
N
0
0
1
1
3
O
N
0
1
0
0
4
O
N
0
1
0
1
5
O
N
0
1
1
0
6
O
N
0
1
1
1
7
O
N
2
5
0
4
S
P
H
N
I
B
D
D
A
A
D
D
A
h
c
ti
w
S
n
O
1
X
X
e
n
o
N
0
0
0
B
,
A
0
O
N
0
0
1
B
,
A
1
O
N
0
1
0
B
,
A
2
O
N
0
1
1
B
,
A
3
O
N
Truth Tables
3
5
0
4
S
P
H
N
I
C
D
D
A
B
D
D
A
A
D
D
A
s
e
h
c
ti
w
S
n
O
1
X
X
X
e
n
o
N
0
0
0
0
C
O
N
B
O
N
A
O
N
0
0
0
1
C
O
N
B
O
N
A
C
N
0
0
1
0
C
O
N
B
C
N
A
O
N
0
0
1
1
C
O
N
B
C
N
A
C
N
0
1
0
0
C
C
N
B
O
N
A
O
N
0
1
0
1
C
C
N
B
O
N
A
C
N
0
1
1
0
C
C
N
B
C
N
A
O
N
0
1
1
1
C
C
N
B
C
N
A
C
N
Logic 0, V
AL
0.8V
Logic 1, V
IH
2.4V
3
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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PS4051/PS4052/PS4053
17V CMOS Analog Multiplexers/Switches
PS8461 02/16/00
Electrical Specifications - Dual Supplies
(V = 5V 10%, GND = 0V, V
AH
= V
IH
= 2.4V, V
AL
= V
IL
= 0.8V)
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1
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m
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4
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4
=
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+
=
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4
PS8461 02/16/00
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PS4051/PS4052/PS4053
17V CMOS Analog Multiplexers/Switches
Notes:
1. The algebraic convention, where most negative value is a minimum and most positive is a maximum, is used in this data sheet.
2. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing.
3. Guaranteed by design
4.
R
=
R
max
- R
min
5. Flatness is defined as the difference between the maximum and minimum values of on-resistance measured over the specific
analog signal range, i.e., V
NO
= 3V to 0 and 0V to 3V.
6. Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at +25C.
7. Off Isolation = 20log
10
V
COM
/ V
NO
. See Figure 5.
Electrical Specifications - Dual Supplies (continued)
(V = 5V 10%, GND = 0V, V
AH
= V
IH
= 2.4V, V
AL
= V
IL
= 0.8V)
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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PS4051/PS4052/PS4053
17V CMOS Analog Multiplexers/Switches
PS8461 02/16/00
r
e
t
e
m
a
r
a
P
l
o
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1
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,
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5
.
3
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(
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(
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V
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,
V
0
=
V
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C
V
5
.
5
=
+
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,
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5
.
4
=
5
2
1
.
0
0
5
n
ll
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)
8
(
I
)
F
F
O
(
M
O
C
,
V
5
.
5
=
+
V
V
M
O
C
,
V
5
.
4
=
V
O
N
r
o
,
V
0
=
V
M
O
C
,
V
0
=
V
O
N
V
5
.
4
=
1
5
0
4
S
P
5
2
1
0
5
ll
u
F
0
1
0
0
1
2
5
0
4
S
P
3
5
0
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2
1
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Electrical Characteristics - Single 5V Supply
(V+ = +5V 10%, V = 0V, GND = 0V, V
AH
= V
IH
= 2.4V, V
AL
= V
IL
= 0.8V)
6
PS8461 02/16/00
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PS4051/PS4052/PS4053
17V CMOS Analog Multiplexers/Switches
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Electrical Characteristics - Single 5V(continued)
(V+ = +5V 10%, V = 0V, GND = 0V, V
AH
= V
IH
= 2.4V, V
AL
= V
IL
= 0.8V)
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p
Electrical Characteristics - Single 3V Supply
(V+ = +3.3V 10%, V = 0V, GND = 0V, V
AH
= V
IH
= +2.4V, V
AL
= V
IL
L
= +0.8V)
Notes:
1. The algebraic convention, where the most negative value is a minimum and the most positive is a maximum, is used
in this data sheet.
2.
Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing.
3. Guaranteed by design
4.
R
=
R
max
- R
min
5. Flatness is defined as the difference between the maximum and minimum value of on-resistance measured.
6. Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at +25C.
7. Worst-case isolation is on channel 4 because of its proximity to the COM pin. Off isolation = 20log V
COM
/V
NO
,
V
COM
= output, VNO = input to off switch
8. Leakage testing at single supply is guaranteed by testing with dual supplies.
7
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PS4051/PS4052/PS4053
17V CMOS Analog Multiplexers/Switches
PS8461 02/16/00
Test Circuits/Timing Diagrams
Figure 1. Transition Time
Figure 2. Switching Times
tr <20ns
tf <20ns
ttrans
VNO7
ON
ttrans
VOUT
VNO0
90%
90%
Logic
Input
Switch
Output
V+
0V
0V
50%
V+
V+
NO7
COM
GND
V-
V+
V-
V-
NO0
ADDC
ADDB
ADDA
INH
NO1-NO6
50
9
V
OUT
300
9
35pF
PS4051
V+
V+
NO3
COM
GND
V-
V+
V-
V-
NO0
ADDB
ADDA
INH
NO1-NO2
50
9
V
OUT
300
9
35pF
PS4052
V+
V+
COM
GND
V-
V-
V+
V-
NO
ADD
INH
NC
50
9
V
OUT
300
9
35pF
PS4053
V+
V+
COM
GND
V-
V+
V-
NO0
ADDX
INH
NOX
50
9
V
OUT
300
9
35pF
tr <20ns
tf <20ns
VOUT
tON
90%
10%
Logic
Input
Switch
Output
V+
0V
0V
50%
PS4051
PS4052
V+
+5V
COM
GND
V-
V+
V-
NO
NC
ADD
INH
50
9
V
OUT
300
9
35pF
V-
PS4053
tOFF
tr <20ns
tf <20ns
VOUT
tON
90%
10%
Logic
Input
Switch
Output
V+
0V
0V
50%
tOFF
V-
8
PS8461 02/16/00
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PS4051/PS4052/PS4053
17V CMOS Analog Multiplexers/Switches
Figure 3. Break-Before-Make Interval
Figure 4. Charge Injection
Figure 5. Off Isolation
Figure 6. Crosstalk
V+
V+
COM
GND
INH
V-
V-
10nF
10nF
NO0
NO1
NO7
ADD
V
OUT
R
L
= 50
9
V
OUT
V
IN
V
IN
R = 1k
9
R
G
= 50
9
CROSSTALK = 20log
~
PS4051
PS4052
50
9
9
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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PS4051/PS4052/PS4053
17V CMOS Analog Multiplexers/Switches
PS8461 02/16/00
Figure 8. NO/COM Capacitance
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
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P
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Q
Ordering Information
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P
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