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Электронный компонент: 10H20EV8

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Philips Semiconductors Programmable Logic Devices
Product specification
10H20EV8/10020EV8
ECL programmable array logic
113
October 22, 1993
8531423 11164
DESCRIPTION
The 10H20EV8/10020EV8 is an ultra
high-speed universal ECL PAL
device.
Combining versatile output macrocells with a
standard AND/OR single programmable
array, this device is ideal in implementing a
user's custom logic. The use of Philips
Semiconductors state-of-the-art bipolar oxide
isolation process enables the
10H20EV8/10020EV8 to achieve optimum
speed in any design. The SNAP design
software package from Philips
Semiconductors simplifies design entry
based upon Boolean or state equations.
The 10H20EV8/10020EV8 is a two-level logic
element comprised of 11 fixed inputs, an
input pin that can either be used as a clock or
12th input, 90 AND gates, and 8 Output Logic
Macrocells. Each Output Macrocell can be
individually configured as a dedicated input,
dedicated output with polarity control, a
bidirectional I/O, or as a registered output
that has both output polarity control and
feedback to the AND array. This gives the
part the capability of having up to 20 inputs
and eight outputs.
The 10H20EV8/10020EV8 has a variable
number of product terms that can be OR'd
per output. Four of the outputs have 12 AND
terms available and the other four have 8
terms per output. This allows the designer the
extra flexibility to implement those functions
that he couldn't in a standard PAL device.
Asynchronous Preset and Reset product
terms are also included for system design
ease. Each output has a separate output
enable product term. Another feature added
for the system designer is a power-up Reset
on all registered outputs.
The 10H20EV8/10020EV8 also features the
ability to Preload the registers to any desired
state during testing. The Preload is not
affected by the pattern within the device, so
can be performed at any step in the testing
sequence. This permits full logical verification
even after the device has been patterned.
FEATURES
Ultra high speed ECL device
t
PD
= 4.5ns (max)
t
IS
= 2.6ns (max)
t
CKO
= 2.3ns (max)
f
MAX
= 208MHz
Universal ECL Programmable Array Logic
8 user programmable output macrocells
Up to 20 inputs and 8 outputs
Individual user programmable output
polarity
Variable product term distribution allows
increased design capability
Asynchronous Preset and Reset capability
10KH and 100K options
Power-up Reset and Preload function to
enhance state machine design and testing
Design support provided via SNAP and
other CAD tools
Security fuse for preventing design
duplication
Available in 24-Pin 300mil-wide DIP and
28-Pin PLCC.
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
F Package
I1
I2
CLK/I12
F1
F2
VCO1
F3
F4
I3
I4
I5
VCC
I11
I10
F8
F7
VCO2
F6
F5
I9
I8
I7
I6
VEE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NC
NC
A Package
F6
F4
I1
I2
CLK/I12
F1
F2
VCO1
NC
F3
I3
I4
I5
I6
I7
I8
I9
F5
F8
F7
VCO2
NC
I10
I11
VCC
VEE
F = Ceramic DIP (300mil-wide)
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
DRAWING NUMBER
24-Pin Ceramic Dual In-Line (300mil-wide)
10H20EV84F
10020EV84F
0586B
28-Pin Plastic Leaded Chip Carrier
10H20EV84A
10020EV84A
0401F
PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices, Inc.
Philips Semiconductors Programmable Logic Devices
Product specification
10H20EV8/10020EV8
ECL programmable array logic
October 22, 1993
114
LOGIC DIAGRAM
1. All unprogrammed or virgin "AND" gate locations are pulled to logic "0"
2.
Programmable connections
3. Pinout for F Package
18
OUTPUT
LOGIC
MACRO
CELL
D
OUTPUT
LOGIC
MACRO
CELL
D
OUTPUT
LOGIC
MACRO
CELL
D
OUTPUT
LOGIC
MACRO
CELL
D
OUTPUT
LOGIC
MACRO
CELL
D
OUTPUT
LOGIC
MACRO
CELL
D
OUTPUT
LOGIC
MACRO
CELL
D
OUTPUT
LOGIC
MACRO
CELL
D
ASYNCHRONOUS RESET
ASYNCHRONOUS PRESET
3
1
2
9
10
11
13
14
15
16
22
23
17
8
7
20
5
21
4
0
4
8
12
16
20
24
28
32
36
INPUT LINES
0
7
0
7
0
7
0
7
0
11
0
11
0
11
0
11
NOTES:
Figure 1. Output Logic Macrocell
Fn
VCC
VCC
CLK
AR
AP
D
Q
Q
S1
S0
OUTPUT
SELECT
MUX
S1
FEEDBACK
MUX
Philips Semiconductors Programmable Logic Devices
Product specification
10H20EV8/10020EV8
ECL programmable array logic
October 22, 1993
115
FUNCTIONAL DIAGRAM
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
OUTPUT
LOGIC
MACROCELL
PROGRAMMABLE AND ARRAY
(90
40)
CLK/I
I
1
11
12
12
12
12
8
8
8
8
RESET
PRESET
F
F
F
F
F
F
F
F
FUNCTIONAL DESCRIPTION
The 10H20EV8/10020EV8 is an ultra
high-speed universal ECL PAL-type device.
Combining versatile Output Macrocells with a
standard AND/OR single programmable
array, this device is ideal in implementing a
user's custom logic.
As can be seen in the Logic Diagram, the
device is a two-level logic element with a
programmable AND array. The 20EV8 can
have up to 20 inputs and 8 outputs. Each
output has a versatile Macrocell whereby the
output can either be configured as a
dedicated input, a dedicated combinatorial
output with polarity control, a bidirectional I/O,
or as a registered output that has both output
polarity control and feedback into the AND
array.
The device also features 90 product terms.
Two of the product terms can be used for a
global asynchronous preset and/or reset.
Eight of the product terms can be used for
individual output enable control of each
Macrocell. The other 80 product terms are
distributed among the outputs. Four of the
outputs have eight product terms, while the
other four have 12. This arrangement allows
the utmost in flexibility when implementing
user patterns.
Output Logic Macrocell
The 10H20EV8/10020EV8 incorporates an
extremely versatile Output Logic Macrocell
that allows the user complete flexibility when
configuring outputs.
As seen in Figure 1, the 10H20EV8/
10020EV8 Output Logic Macrocell consists of
an edge-triggered D-type flip-flop, an output
select MUX, and a feedback select MUX.
Fuses S
0
and S
1
allow the user to select
between the various cells. S
1
controls
whether the output will be either registered
with internal feedback or combinatorial I/O.
S
0
controls the polarity of the output (Active-
HIGH or Active-LOW). This allows the user to
achieve the following configurations:
Registered Active-HIGH output, Registered
Active-LOW output, Combinatorial Active-
HIGH output, and Combinatorial Active-LOW
output. With the output enable product term,
this list can be extended by adding the
configurations of a Combinatorial I/O with
Polarity or another input.
Philips Semiconductors Programmable Logic Devices
Product specification
10H20EV8/10020EV8
ECL programmable array logic
October 22, 1993
116
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
PARAMETER
RATING
UNIT
V
EE
Supply voltage
8.0
V
V
IN
Input voltage (V
IN
should never be more negative than V
EE
)
0 to V
EE
V
I
O
Output source current
50
mA
T
S
Operating Temperature range
55 to +150
C
T
J
Storage Temperature range
Ceramic Package
+165
C
Plastic Package
+150
C
NOTE:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at
these or any other condition above those indicated in the operational and programming specification of the device is not implied.
DC OPERATING CONDITIONS 10H20EV8
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
V
CC
, V
CO1
, V
CO2
Circuit ground
0
0
0
V
V
EE
Supply voltage (negative)
5.2
V
T
amb
= 0
C
1170
840
mV
V
IH
High level input voltage
T
amb
= +25
C
1130
810
mV
T
amb
= +75
C
1070
735
mV
T
amb
= 0
C
1950
1480
mV
V
IL
Low level input voltage
T
amb
= +25
C
1950
1480
mV
T
amb
= +75
C
1980
1450
mV
T
amb
Operating ambient temperature range
0
+25
+75
C
NOTE:
When operating at other than the specified V
EE
voltage (5.2V), the DC and AC Electrical Characteristics will vary slightly from specified values.
DC OPERATING CONDITIONS 10020EV8
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
V
CC
, V
CO1
, V
CO2
Circuit ground
0
0
0
V
V
EE
Supply voltage
4.8
4.5
4.2
V
V
EE
Supply voltage when opetating with the 10K
or 10KH ECL family
5.7
V
V
EE
= 4.2V
1150
V
IH
High level input voltage
V
EE
= 4.5V
1165
880
mV
V
EE
= 4.8V
1165
V
EE
= 4.2V
1475
mV
V
IL
Low level input voltage
V
EE
= 4.5V
1810
1475
mV
V
EE
= 4.8V
1490
mV
T
amb
Operating ambient temperature range
0
+25
+85
C
NOTE:
When operating at other than the specified V
EE
voltages (4.2V, 4.5V, 4.8V), the DC and AC Electrical Characteristics will vary slightly from
their specified values.
Philips Semiconductors Programmable Logic Devices
Product specification
10H20EV8/10020EV8
ECL programmable array logic
October 22, 1993
117
D
AP
AR
D
Q
CK
Q
D
AP
AR
D
Q
CK
Q
Registered Active-HIGH
Registered Active-LOW
D
Combinatorial Active-HIGH
Figure 2. Output Macro Cell Configurations
D
Combinatorial Active-LOW
OUTPUT MACRO CELL
CONFIGURATION
Shown in Figure 2 are the four possible
configurations of the output macrocell using
fuses S
0
and S
1
. As seen, the output can
either be registered Active-HIGH/LOW with
feedback or combinatorial Active-HIGH/LOW
with feedback. If the registered mode is
chosen, the feedback from the Q output to
the AND array enables one to make state
machines or shift registers without having to
tie the output to one of the inputs. If a
combinatorial output is chosen, the feedback
gate is enabled from the pin and allows one
to create permanent outputs, permanent
inputs, or I/O pins through the use of the
output enable (D) product term.
OUTPUT ENABLE
Each output on the 10H20EV8/10020EV8
has its own individual product term for output
enable. The use of the D product term
(direction control) allows the user three
possible configurations of the outputs. They
are: always enabled, always disabled, and
controlled by a programmed pattern. A HIGH
on the D term enables the output, while a
LOW performs the disable function. Output
enable control can be achieved by
programming a pattern on the D term.
The output enable control can also be used
to expand a designer's possibilities once a
combinatorial output has been chosen. If the
D term is always HIGH, the pin becomes a
permanent Active-HIGH/LOW output. If the
D term is always LOW (all fuses left intact),
the pin now becomes an extra input.
PRESET AND RESET
The 10H20EV8/10020EV8 also includes a
separate product term for asynchronous
Preset and asynchronous Reset. These lines
are common for all registers and are asserted
when the specific product term goes HIGH.
Being asynchronous, they are independent of
the clock. It should be noted that the actual
state of the output is dependent on how the
polarity of the particular output has been
chosen. If the outputs are a mix of
Active-HIGH and Active-LOW, a Preset
signal will force the Active-HIGH outputs
HIGH while the Active-LOW outputs would go
LOW, even though the Q output of all
flip-flops would go HIGH. A Reset signal
would force the opposite conditions.
PRELOAD
To simplify testing, the 10H20EV8/10020EV8
has also included PRELOAD circuitry. This
allows a user to load any particular data
desired into the registers regardless of the
programmed pattern. This means that the
PRELOAD can be done on a blank part and
after that same part has been programmed to
facilitate any post-fuse testing desired.
It can also be used by a designer to help
debug a circuit. This could be important if a
state machine was implemented in the
10H20EV8/ 10020EV8. The PRELOAD
would allow the entry of any state in the
sequence desired and start clocking from that
particular point. Any or all transitions could be
verified.