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Электронный компонент: 74ABT16260DL

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Philips
Semiconductors
74ABT16260/74ABTH16260
12-bit to 24-bit multiplexed D-type latches
(3-State)
Product specification
Supersedes data of 1996 Nov 20
IC23 Data Handbook
1998 Feb 10
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74ABT16260
74ABTH16260
12-bit to 24-bit multiplexed D-type latches (3-State)
2
1998 Feb 10
853-2048-18945
FEATURES
ESD protection exceeds 2000V per Mil-Std-883C, Method 3015;
exceeds 200V using machine model (C = 200pF, R = 0).
Latch-up performance exceeds 500mA per JEDEC Standard
JESD-17.
Distributed V
CC
and GND pin configuration minimizes high-speed
switching noise.
Flow-through architecture optimizes PCB layout.
High-drive outputs (32mA I
OH
, 64mA I
OL
).
74ABTH16260 incorporates bus-hold inputs which eliminate the
need for external pull-up resistors.
Package options:
56-pin plastic Shrink Small-Outline Package (SSOP)
56-pin plastic Thin Shrink Small-Outline Package (TSSOP)
DESCRIPTION
The 74ABT16260/74ABTH16260 is a 12-bit to 24-bit multiplexed
D-type latch used in applications where two separate data paths
must be multiplexed onto, or demultiplexed from, a single data path.
Typical applications include multiplexing and/or demultiplexing of
address and data information in microprocessor or bus-interface
applications. This device is alto useful in memory-interleaving
applications.
Three 12-bit I/O ports (A1A12, 1B11B12, and 2B12B12) are
available for address and/or data transfer. The output enable (OE1B,
OE2B, and OEA) inputs control the bus transceiver functions. The
OE1B and OE2B control signals also allow bank control in the A to
B direction.
Address and/or data information can be stored using the internal
storage latches. The latch enable (LE1B, LE2B, LEA1B, and
LEA2B) inputs are used to control data storage. When the latch
enable input is high, the latch is transparent. When the latch enable
input goes low, the data present at the inputs is latched and remains
latched until the latch enable input is returned high.
To ensure the high-impedance state during power-up or
power-down, OE should be tied to V
CC
through a pull-up resistor;
the minimum value of the resistor is determined by the current
sinking capability of the driver.
The 74ABTH incorporates the bus hold feature. The 74ABT does
not include bus hold feature. Both parts are available in 56-pin
SSOP and TSSOP.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
C; GND = 0V
TYPICAL
UNIT
t
PLH
Propagation delay
C = 50 pF
2.8
ns
t
PHL
nAx to nBx nBx to nAx
C
L
= 50 pF
2.5
ns
C
IN
Input capacitance
V
I
= 0 V or V
CC
4
pF
C
OUT
Output capacitance
V
I/O
= 0 V or 5.0 V
6
pF
I
CCZ
Total supply current
Outputs disabled
100
A
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
40
C to +85
C
74ABT16260 DL
BT16260 DL
SOT371-1
56-Pin Plastic TSSOP Type II
40
C to +85
C
74ABT16260 DGG
BT16260 DGG
SOT364-1
56-Pin Plastic SSOP Type III
40
C to +85
C
74ABTH16260 DL
BH16260 DL
SOT371-1
56-Pin Plastic TSSOP Type II
40
C to +85
C
74ABTH16260 DGG
BH16260 DGG
SOT364-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21
An
Data inputs/outputs (A)
23, 24, 26, 31, 33, 34, 36, 37, 38, 40, 41, 42
1Bn
Data inputs/outputs (B1)
6, 5, 3, 54, 52, 51, 49, 48, 47, 45, 44, 43
2Bn
Data inputs/outputs (B2)
1, 29, 56
OEA, OE1B, OE2B
Output enable input (active low)
2, 27, 30, 55
LE1B, LE2B, LEA1B, LEA2B
Latch enable inputs
Philips Semiconductors
Product specification
74ABT16260
74ABTH16260
12-bit to 24-bit multiplexed D-type latches (3-State)
1998 Feb 10
3
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
45
46
47
48
49
50
51
52
53
54
55
56
OEA
2B3
GND
2B2
2B1
V
CC
A1
A2
A3
GND
OE2B
LEA2B
2B4
GND
2B5
2B6
V
CC
2B8
2B7
2B9
GND
2B10
A4
13
14
15
16
17
18
39
40
41
42
43
44
A5
A6
A7
A8
A9
2B11
1B12
2B12
1B11
1B10
GND
19
38
GND
A10
20
21
22
23
24
25
32
33
34
35
36
37
A11
A12
V
CC
1B1
1B2
1B9
V
CC
1B8
1B6
1B5
GND
GND
26
31 1B4
1B3
27
30 LEA1B
LE2B
28
29
SEL
OE1B
LE1B
1B7
SA00435
FUNCTION TABLES
B to A (OEB = H)
INPUTS
OUTPUT
1B
2B
SEL
LE1B
LE2B
OEA
A
H
X
H
H
X
L
H
L
X
H
H
X
L
L
X
X
H
L
X
L
A0
X
H
L
X
H
L
H
X
L
L
X
H
L
L
X
X
L
X
L
L
A0
X
X
X
X
X
H
Z
A to B (OEA = H)
INPUTS
OUTPUT
A
LEA1B
LEA2B
OE1B
OE2B
1B
2B
H
H
H
L
L
H
H
L
H
H
L
L
L
L
H
H
L
L
L
H
2B0
L
H
L
L
L
L
2B0
H
L
H
L
L
1B0
H
L
L
H
L
L
1B0
L
X
L
L
L
L
1B0
2B0
X
X
X
H
H
Z
Z
X
X
X
L
H
Active
Z
X
X
X
H
L
Z
Active
X
X
X
L
L
Active
Active
Philips Semiconductors
Product specification
74ABT16260
74ABTH16260
12-bit to 24-bit multiplexed D-type latches (3-State)
1998 Feb 10
4
LOGIC DIAGRAM (POSITIVE LOGIC)
G1
1
1
C1
1D
C1
1D
C1
1D
C1
1D
LE1B
LE2B
LEA1B
LEA2B
OE2B
OE1B
OEA
SEL
A1
2
27
30
55
56
29
1
28
8
2B1
1B1
23
6
TO 11 OTHER CHANNELS
SA00436
Philips Semiconductors
Product specification
74ABT16260
74ABTH16260
12-bit to 24-bit multiplexed D-type latches (3-State)
1998 Feb 10
5
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise specified)
1
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
V
CC
Supply voltage range
0.5
7
V
V
I
Input voltage range
see Note 2
0.5
7
V
V
O
Voltage range applied to any output in the high state or power-off state
0.5
5.5
V
I
O
Current into any output in the low state
128
mA
I
IK
Input clamp current
V
I
< 0
18
mA
I
OK
Output clamp current
V
O
< 0
50
mA
Maximum power dissipation at T
amb
= 55
C (in still air)
see Note 3
1.4
W
T
stg
Storage temperature range
65
+150
C
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating
Conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature of 150
C and a board trace length of 750 mils.
RECOMMENDED OPERATING CONDITIONS
1
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
MAX
UNIT
V
CC
Supply voltage
4.5
5.5
V
V
IH
High-level input voltage
2
V
V
IL
Low-level input voltage
0.8
V
V
I
Input voltage
0
V
CC
V
I
OH
High-level output current
32
mA
I
OL
Low-level output current
64
mA
t
/v
Input transition rise or fall rate
Outputs enabled
10
ns/V
t
/V
CC
Power-up ramp rate
200
s/V
T
amb
Operating free-air temperature
40
+85
C
NOTE:
1. Unused or floating inputs must be held high or low.