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Электронный компонент: 74ABT16841A

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Philips
Semiconductors
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
Product specification
Supersedes data of 1995 Sep 28
IC23 Data Handbook
1998 Feb 27
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
2
1998 Feb 27
853-1797 19025
FEATURES
High speed parallel latches
Live insertion/extraction permitted
Extra data width for wide address/data paths or buses carrying
parity
Power-up 3-State
74ABTH16841A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
Power-up reset
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Output capability: +64mA/32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ABT16841A Bus interface latch is designed to provide extra
data width for wider data/address paths of buses carrying parity.
The 74ABT16841A consists of two sets of ten D-type latches with
3-State outputs. The flip-flops appear transparent to the data when
Latch Enable (nLE) is High. This allows asynchronous operation, as
the output transition follows the data in transition. On the nLE
High-to-Low transition, the data that meets the setup and hold time
is latched.
Data appears on the bus when the Output Enable (nOE) is Low.
When nOE is High the output is in the High-impedance state.
Two options are available, 74ABT16841A which does not have the
bus-hold feature and 74ABTH16841A which incorporates the
bus-hold feature.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
nDx to nQx
C
L
= 50pF; V
CC
= 5V
3.1
2.2
ns
C
IN
Input capacitance
V
I
= 0V or V
CC
4
pF
C
OUT
Output capacitance
V
O
= 0V or V
CC
; 3-State
7
pF
I
CCZ
Quiescent supply current
Outputs disabled; V
CC
= 5.5V
500
A
I
CCL
Quiescent supply current
Outputs LOW; V
CC
= 5.5V
10
mA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
40
C to +85
C
74ABT16841A DL
BT16841A DL
SOT371-1
56-Pin Plastic TSSOP Type II
40
C to +85
C
74ABT16841A DGG
BT16841A DGG
SOT364-1
56-Pin Plastic SSOP Type III
40
C to +85
C
74ABTH16841A DL
BH16841A DL
SOT371-1
56-Pin Plastic TSSOP Type II
40
C to +85
C
74ABTH16841A DGG
BH16841A DGG
SOT364-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
55, 54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
1D0 1D9
2D0 2D9
Data inputs
2, 3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
1Q0 1Q9
2Q0 2Q9
Data outputs
1, 28
1OE, 2OE
Output enable inputs (active-Low)
56, 29
1LE, 2LE
Latch enable inputs (active rising edge)
4, 11, 18, 25, 32, 39, 46, 53
GND
Ground (0V)
7, 22, 35, 50
V
CC
Positive supply voltage
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
1998 Feb 27
3
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE
1Q0
1Q1
GND
1Q2
1Q3
1Q4
1Q5
GND
1Q6
1Q7
1Q8
2Q2
1Q9
VCC
2Q3
VCC
2Q1
2Q4
2Q8
2OE
2Q7
1LE
1D0
1D1
GND
1D2
1D3
1D4
1D5
2D0
1D6
1D7
2D1
2D2
GND
2D4
VCC
2D5
VCC
2D3
2D6
GND
2D8
2LE
2D7
SA00076
2Q0
GND
2Q5
28
27
26
25
49
50
51
52
53
54
55
56
2D9
1D9
1D8
GND
2Q9
GND
2Q6
LOGIC SYMBOL
1D0 1D1 1D2 1D3 1D4 1D5 1D6
1D7
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6
1Q7
1D8
1D9
1Q8
1Q9
2D0 2D1 2D2 2D3 2D4 2D5 2D6
2D7
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6
2Q7
2D8
2D9
2Q8
2Q9
55
54
52
51
49
48
47
45
44
43
56
1
29
28
2
3
5
6
8
9
10
12
13
14
42
41
40
38
37
36
34
33
31
30
15
16
17
19
20
21
23
24
26
27
SH00023
1LE
1OE
2LE
2OE
LOGIC SYMBOL (IEEE/IEC)
EN4
2
EN2
4
SH00081
1
56
28
29
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
1D
3D
C1
C3
1OE
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q2
1Q9
2Q3
2Q1
2Q4
2Q8
2OE
2Q7
2Q0
2Q5
2Q9
2Q6
1LE
1D0
1D1
1D2
1D3
1D4
1D5
2D0
1D6
1D7
2D1
2D2
2D4
2D5
2D3
2D6
2D8
2LE
2D7
2D9
1D9
1D8
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
nOE
nLE
nDx
nQ0 nQ9
OPERATING MODE
L
L
H
H
L
H
L
H
Transparent
L
L
l
h
L
H
Latched
H
X
X
Z
High impedance
L
L
X
NC
Hold
H = High voltage level
h
= High voltage level one set-up time prior to the High-to-Low LE
transition
L
= Low voltage level
l
= Low voltage level one set-up time prior to the High-to-Low LE
transition
= High-to-Low LE transition
NC= No change
X = Don't care
Z = High impedance "off" state
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
1998 Feb 27
4
LOGIC DIAGRAM
L
Q
D
nD0
nQ0
nLE
nOE
D
nD1
nQ1
D
nD2
nQ2
D
nD3
nQ3
D
nD4
nQ4
D
nD5
nQ5
D
nD6
nQ6
D
nD7
nQ7
D
nD8
nQ8
D
nD9
nQ9
SH00024
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +7.0
V
I
IK
DC input diode current
V
I
< 0
18
mA
V
I
DC input voltage
3
1.2 to +7.0
V
I
OK
DC output diode current
V
O
< 0
50
mA
V
OUT
DC output voltage
3
Output in Off or High state
0.5 to +5.5
V
I
O
DC output current
Output in Low state
128
mA
I
OUT
DC output current
Output in High state
64
mA
T
stg
Storage temperature range
65 to 150
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
Min
Max
UNIT
V
CC
DC supply voltage
4.5
5.5
V
V
I
Input voltage
0
V
CC
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level Input voltage
0.8
V
I
OH
High-level output current
32
mA
I
OL
Low-level output current
64
mA
t/
v
Input transition rise or fall rate
0
5
ns/V
T
amb
Operating free-air temperature range
40
+85
C
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
1998 Feb 27
5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
C
T
amb
= -40
C
to +85
C
UNIT
Min
Typ
Max
Min
Max
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= -18mA
0.9
1.2
1.2
V
V
CC
= 4.5V; I
OH
= -3mA; V
I
= V
IL
or V
IH
2.5
2.9
2.5
V
V
OH
High-level output voltage
V
CC
= 5.0V; I
OH
= -3mA; V
I
= V
IL
or V
IH
3.0
3.4
3.0
V
V
CC
= 4.5V; I
OH
= -32mA; V
I
= V
IL
or V
IH
2.0
2.4
2.0
V
V
OL
Low-level output voltage
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
0.42
0.55
0.55
V
V
RST
Power-up output voltage
3
V
CC
= 5.5V; I
O
= 1mA; V
I
= GND or V
CC
0.13
0.55
0.55
V
Input leakage current
I
I
In ut leakage current
74ABT16841A
V
CC
= 5.5V; V
I
= V
CC
or GND
0.01
1
1.0
A
I
74ABT16841A
CC
I
CC
Input leakage current
V
CC
= 5.5V; V
I
= V
CC
or GND
Control pins
0.01
1
1
A
I
I
Input leakage current
74ABTH16841A
V
CC
= 5.5V; V
I
= V
CC
Data pins
5
0.01
1
1
A
74ABTH16841A
V
CC
= 5.5V; V
I
= 0
Data ins
5
2
3
5
A
Bus Hold current inputs
6
V
CC
= 4.5V; V
I
= 0.8V
35
35
I
HOLD
Bus Hold current inputs
6
74ABTH16841A
V
CC
= 4.5V; V
I
= 2.0V
75
75
A
74ABTH16841A
V
CC
= 5.5V; V
I
= 0 to 5.5V
800
I
OFF
Power-off leakage current
V
CC
= 0.0V; V
O
or V
I
4.5V
5.0
100
100
A
I
PU/PD
Power-up/down 3-State
output current
4
V
CC
= 2.1V; V
O
= 0.5V; V
I
= GND or V
CC
;
V
OE
= Don't care
5.0
50
50
A
I
OZH
3-State output High current
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
5.0
10
10
A
I
OZL
3-State output Low current
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
5.0
10
10
A
I
CEX
Output High leakage current
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
5.0
50
50
A
I
O
Output current
1
V
CC
= 5.5V; V
O
= 2.5V
50
70
180
50
180
mA
I
CCH
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
0.5
1
1
mA
I
CCL
Quiescent supply current
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
10
19
19
mA
I
CCZ
V
CC
= 5.5V; Outputs 3-State; V
I
= GND or V
CC
0.5
1
1
mA
I
CC
Additional supply current per
input pin
2
V
CC
= 5.5V; one input at 3.4V, other inputs at
V
CC
or GND
0.2
1
1
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0V and 2.1V with a transition time of up to 10msec. From V
CC
= 2.1V to V
CC
= 5V
10% a
transition time of up to 100
sec is permitted.
5. Unused pins at V
CC
or GND.
6. This is the bus hold overdrive current required to force the input to the opposite logic state.
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
T
amb
= -40 to +85
o
C
V
CC
= +5.0V
0.5V
UNIT
MIN
TYP
MAX
MIN
MAX
t
PLH
t
PHL
Propagation delay
nDx to nQx
2
1.1
1.5
3.1
2.2
4.1
3.1
1.1
1.5
4.9
3.6
ns
t
PLH
t
PHL
Propagation delay
nLE to nQx
1
1.5
1.0
2.5
2.1
3.3
2.8
1.5
1.0
3.7
3.1
ns
t
PZH
t
PZL
Output enable time
to High and Low level
4
5
1.2
1.2
2.4
2.2
3.2
2.9
1.2
1.2
4.0
3.6
ns
t
PHZ
t
PLZ
Output disable time
from High and Low level
4
5
1.8
1.5
3.0
2.5
4.0
3.2
1.8
1.5
4.9
3.7
ns