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Электронный компонент: 74ABT374APWDH

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Philips Semiconductors
Product specification
74ABT374A
Octal D-type flip-flop; positive-edge trigger
(3-State)
1
1995 Sep 06
853-1448 15704
FEATURES
8-bit positive edge triggered register
3-State output buffers
Output capability: +64mA/32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Power-up 3-State
Power-up reset
Live insertion/extraction permitted
DESCRIPTION
The 74ABT374A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT374A is an 8-bit, edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE) control
gates.
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop's Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the clock operation.
When OE is Low, the stored data appears at the outputs. When OE
is High, the outputs are in the High-impedance "OFF" state, which
means they will neither drive nor load the bus.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
CP to Qn
C
L
= 50pF; V
CC
= 5V
3.4
3.8
ns
C
IN
Input capacitance
V
I
= 0V or V
CC
4
pF
C
OUT
Output capacitance
Outputs disabled; V
O
= 0V or V
CC
7
pF
I
CCZ
Total supply current
Outputs disabled; V
CC
=5.5V
110
A
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
20-Pin Plastic DIP
40
C to +85
C
74ABT374A N
74ABT374A N
SOT146-1
20-Pin plastic SO
40
C to +85
C
74ABT374A D
74ABT374A D
SOT163-1
20-Pin Plastic SSOP Type II
40
C to +85
C
74ABT374A DB
74ABT374A DB
SOT339-1
20-Pin Plastic TSSOP Type I
40
C to +85
C
74ABT374A PW
74ABT374APW DH
SOT360-1
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
Q4
GND
D4
D5
Q5
Q6
D6
D7
Q7
VCC
CP
SA00110
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1
OE
Output enable input (active-Low)
3, 4, 7, 8,
13, 14, 17,
18
D0-D7
Data inputs
2, 5, 6, 9,
12, 15, 16,
19
Q0-Q7
Data outputs
11
CP
Clock pulse input (active rising edge)
10
GND
Ground (0V)
20
V
CC
Positive supply voltage
Philips Semiconductors
Product specification
74ABT374A
Octal D-type flip-flop; positive-edge trigger
(3-State)
1995 Sep 06
2
LOGIC SYMBOL
3
4
7
8
13
14
18
17
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2
5
6
9
12 15 16
19
1
11
SA00111
CP
OE
LOGIC SYMBOL (IEEE/IEC)
11
3
2
4
5
7
6
8
9
C1
13
12
14
15
17
16
18
19
1
EN
1D
SA00112
FUNCTION TABLE
INPUTS
INTERNAL
OUTPUTS
OPERATING MODE
OE
CP
Dn
INTERNAL
REGISTER
Q0 Q7
OPERATING MODE
L
l
L
L
Latch and read register
L
h
H
H
Latch and read register
L
X
NC
NC
Hold
H
X
NC
Z
Disable outputs
H
Dn
Dn
Z
Disable outputs
H = High voltage level
h
= High voltage level one set-up time prior to the Low-to-High clock transition
L
= Low voltage level
l
= Low voltage level one set-up time prior to the Low-to-High clock transition
NC= No change
X = Don't care
Z = High impedance "off" state
= Low-to-High clock transition
= not a Low-to-High clock transition
LOGIC DIAGRAM
CP Q
D
D0
Q0
CP Q
D
D1
CP Q
D
D2
CP Q
D
D3
CP Q
D
D4
CP Q
D
D5
CP Q
D
D6
CP Q
D
D7
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
OE
SA00113
3
4
7
8
13
14
17
18
11
1
2
5
6
9
12
15
16
19
Philips Semiconductors
Product specification
74ABT374A
Octal D-type flip-flop; positive-edge trigger
(3-State)
1995 Sep 06
3
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +7.0
V
I
IK
DC input diode current
V
I
< 0
18
mA
V
I
DC input voltage
3
1.2 to +7.0
V
I
OK
DC output diode current
V
O
< 0
50
mA
V
OUT
DC output voltage
3
output in Off or High state
0.5 to +5.5
V
I
OUT
DC output current
output in Low state
128
mA
T
stg
Storage temperature range
65 to 150
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
MAX
UNIT
V
CC
DC supply voltage
4.5
5.5
V
V
I
Input voltage
0
V
CC
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
I
OH
High-level output current
32
mA
I
OL
Low-level output current
64
mA
t/
v
Input transition rise or fall rate
0
10
ns/V
T
amb
Operating free-air temperature range
40
+85
C
Philips Semiconductors
Product specification
74ABT374A
Octal D-type flip-flop; positive-edge trigger
(3-State)
1995 Sep 06
4
DC ELECTRICAL CHARACTERISTICS
SYMBOL
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
C
T
amb
= 40
C
to +85
C
UNIT
MIN
TYP
MAX
MIN
MAX
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= 18mA
0.9
1.2
1.2
V
V
CC
= 4.5V; I
OH
= 3mA; V
I
= V
IL
or V
IH
2.5
2.9
2.5
V
V
OH
High-level output voltage
V
CC
= 5.0V; I
OH
= 3mA; V
I
= V
IL
or V
IH
3.0
3.4
3.0
V
V
CC
= 4.5V; I
OH
= 32mA; V
I
= V
IL
or V
IH
2.0
2.4
2.0
V
V
OL
Low-level output voltage
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
0.42
0.55
0.55
V
V
RST
Power-up output low voltage
3
V
CC
= 5.5V; I
O
= 1mA; V
I
= GND or V
CC
0.13
0.55
0.55
V
I
I
Input leakage current
V
CC
= 5.5V; V
I
= GND or 5.5V
0.01
1.0
1.0
A
I
OFF
Power-off leakage current
V
CC
= 0.0V; V
O
or V
I
4.5V
5.0
100
100
A
I
PU
/I
PD
Power-up/down 3-State
output current
V
CC
= 0.0V; I
O
= 1mA; V
I
= GND or V
CC
;
V
OE
= Don't Care
5.0
50
50
A
I
OZH
3-State output High current
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
5.0
50
50
A
I
OZL
3-State output Low current
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
5.0
50
50
A
I
CEX
Output High leakage current
V
CC
= 5.5V; V
O
= 0.5V; V
I
= GND or V
CC
5.0
50
50
A
I
O
Output current
1
V
CC
= 5.5V; V
O
= 2.5V
50
100
180
50
180
mA
I
CCH
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
110
250
250
A
I
CCL
Quiescent supply current
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
24
30
30
mA
I
CCZ
V
CC
= 5.5V; Outputs 3State;
V
I
= GND or V
CC
110
250
250
A
I
CC
Additional supply current per
input pin
2
V
CC
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
0.5
1.5
1.5
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
T
amb
= -40 to
+85
o
C
V
CC
= +5.0V
0.5V
UNIT
Min
Typ
Max
Min
Max
f
MAX
Maximum clock frequency
1
200
300
200
ns
t
PLH
t
PHL
Propagation delay
CP to Qn
1
1.7
2.0
3.4
3.8
4.5
4.9
1.7
2.0
5.1
5.2
ns
t
PZH
t
PZL
Output enable time
to High and Low level
3
4
1.2
2.2
3.5
4.3
4.5
5.4
1.2
2.2
5.4
6.2
ns
t
PHZ
t
PLZ
Output disable time
from High and Low level
3
4
1.8
1.5
3.6
3.0
4.7
4.1
1.8
1.5
5.2
4.3
ns
Philips Semiconductors
Product specification
74ABT374A
Octal D-type flip-flop; positive-edge trigger
(3-State)
1995 Sep 06
5
AC SETUP REQUIREMENTS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
T
amb
= -40 to +85
o
C
V
CC
= +5.0V
0.5V
UNIT
Min
Typ
Min
t
s
(H)
t
s
(L)
Setup time, High or Low
Dn to CP
2
1.5
1.2
0.6
0.3
1.5
1.2
ns
t
h
(H)
t
h
(L)
Hold time, High or Low
Dn to CP
2
1.0
1.0
0.3
0.5
1.0
1.0
ns
t
w
(H)
t
w
(L)
CP pulse width
High or Low
1
2.0
2.8
0.8
1.0
2.0
2.8
ns
AC WAVEFORMS
V
M
= 1.5V, V
IN
= GND to 3.0V
VM
VM
VM
VM
VM
1/fMAX
tw(H)
tw(L)
tPHL
tPLH
CP
Qn
SA00056
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
V
M
Dn
V
M
V
M
V
M
V
M
V
M
CP
t
s
(H)
t
h
(H)
t
s
(L)
t
h
(L)
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SA00107
Waveform 2. Data Setup and Hold Times
OE
V
M
t
PZH
t
PHZ
0V
Qn
V
M
V
M
SA00066
V
OH
0.3V
Waveform 3. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
OE
t
PZL
t
PLZ
0V
Qn
V
M
V
M
V
M
SA00067
V
OL
+0.3V
Waveform 4. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
Philips Semiconductors
Product specification
74ABT374A
Octal D-type flip-flop; positive-edge trigger
(3-State)
1995 Sep 06
6
TEST CIRCUIT AND WAVEFORM
PULSE
GENERATOR
RT
VIN
VOUT
CL
RL
VCC
RL
7.0V
Test Circuit for 3-State Outputs
VM
VM
tW
AMP (V)
NEGATIVE
PULSE
10%
10%
90%
90%
0V
VM
VM
tW
AMP (V)
POSITIVE
PULSE
90%
90%
10%
10%
0V
tTHL (tF)
tTLH (tR)
tTHL (tF)
tTLH (tR)
V
M
= 1.5V
Input Pulse Definition
DEFINITIONS
R
L
=
Load resistor; see AC CHARACTERISTICS for value.
C
L
=
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
R
T
=
Termination resistance should be equal to Z
OUT
of
pulse generators.
INPUT PULSE REQUIREMENTS
FAMILY
Amplitude
Rep. Rate
t
W
t
R
t
F
74ABT
3.0V
1MHz
500ns
2.5ns
2.5ns
SWITCH POSITION
TEST
SWITCH
t
PLZ
closed
t
PZL
closed
All other
open
SA00012
D.U.T.