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Электронный компонент: 74ABT651PW

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Philips Semiconductors
Product specification
74ABT651
Octal transceiver/register, inverting (3-State)
1
1995 Sep 06
853-1783 15703
FEATURES
Independent registers for A and B buses
The 74ABT651 is the inverting version of the 74ABT652
Multiplexed real-time and stored data
3-State outputs
Live insertion/extraction permitted.
Power-up 3-State
Power-up reset
Output capability: +64mA/32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT651 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT651 transceiver/register consists of bus transceiver
circuits with 3-State outputs, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data directly from the input
bus or the internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes High. Output
Enable (OEAB, OEBA) and Select (SAB, SBA) pins are provided for
bus management.
The following examples demonstrate the four fundamental
bus-management functions that can be performed with the
74ABT651.
The select pins determine whether data is stored or transferred
through the device in real time.
The output enable pins determine the direction of the data flow.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
CPBA to An or CPAB to Bn
C
L
= 50pF; V
CC
= 5V
3.8
4.4
ns
C
IN
Input capacitance
V
I
= 0V or V
CC
4
pF
C
I/O
I/O capacitance
Outputs disabled; V
O
= 0V or V
CC
7
pF
I
CCZ
Total supply current
Outputs disabled; V
CC
=5.5V
110
A
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
24-Pin Plastic DIP
40
C to +85
C
74ABT651 N
74ABT651 N
SOT222-1
24-Pin plastic SO
40
C to +85
C
74ABT651 D
74ABT651 D
SOT137-1
24-Pin Plastic SSOP Type II
40
C to +85
C
74ABT651 DB
74ABT651 DB
SOT340-1
24-Pin Plastic TSSOP Type I
40
C to +85
C
74ABT651 PW
74ABT651PW DH
SOT355-1
PIN CONFIGURATION
SA00094
CPAB
SAB
OEAB
A0
A1
A2
A3
A4
A5
A6
A7
GND
1
2
3
4
5
6
7
8
9
10
11
12
V
CC
CPBA
SBA
OEBA
B0
B1
B2
B3
B4
B5
B6
B7
13
14
15
16
17
18
19
20
21
22
23
24
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1, 23
CPAB /
CPBA
A to B clock input / B to A clock input
2, 22
SAB /
SBA
A to B select input / B to A select input
3, 21
OEAB /
OEBA
A to B Output Enable input /
B to A Output Enable input
(activeLow)
4, 5, 6, 7, 8,
9, 10, 11
A0 A7
Data inputs/outputs (A side)
20, 19, 18,
17, 16, 15,
14, 13
B0 B7
Data inputs/outputs (B side)
12
GND
Ground (0V)
24
V
CC
Positive supply voltage
Philips Semiconductors
Product specification
74ABT651
Octal transceiver/register, inverting (3-State)
1995 Sep 06
2
LOGIC SYMBOL (IEEE/IEC)
SA00125
21
3
23
22
1
2
4
5
6
7
8
9
10
11
EN1 [BA]
EN2 [AB]
C4
G7
C6
G5
20
19
18
17
16
15
14
13
w
1
1
5
4D
5 1
w
1
2
6D 7
1
7
LOGIC SYMBOL
23
CPBA
22
SBA
21
OEBA
CPAB
1
SAB
2
SA00095
B0
B1
B2
B3
B4
B5
B6
B7
20
19
18
17
16
15
14
13
4
5
6
7
8
9
10
11
A0
A1
A2
A3
A4
A5
A6
A7
3
OEAB
}
REAL TIME BUS TRANSFER
BUS B TO BUS A
OEAB OEBA CPAB CPBA SAB SBA
L
L
X
X
X
L
}
REAL TIME BUS TRANSFER
BUS A TO BUS B
OEAB OEBA CPAB CPBA SAB SBA
H
H
X
X
L
X
}
STORAGE FROM
A, B, OR A AND B
OEAB OEBA CPAB CPBA SAB SBA
X
H
X
X
X
L
X
X
X
X
L
H
X
X
}
TRANSFER STORED DATA
TO A OR B
OEAB OEBA CPAB CPBA SAB SBA
H
L
H | L H | L
H
H
SA00097
A
B
A
B
A
B
A
B
Philips Semiconductors
Product specification
74ABT651
Octal transceiver/register, inverting (3-State)
1995 Sep 06
3
FUNCTION TABLE
INPUTS
DATA I/O
OPERATING MODE
OEAB
OEBA
CPAB
CPBA
SAB
SBA
An
Bn
OPERATING MODE
L
L
H
H
H or L
H or L
X
X
X
X
Input
Input
Isolation
Store A and B data
X
H
H
H
H or L
X
**
X
X
Input
Unspecified
output*
Store A, Hold B
Store A in both registers
L
L
X
L
H or L
X
X
X
**
Unspecified
output*
Input
Hold A, Store B
Store B in both registers
L
L
L
L
X
X
X
H or L
X
X
L
H
Output
Input
Real time B data to A bus
Stored B data to A bus
H
H
H
H
X
H or L
X
X
L
H
X
X
Input
Output
Real time A data to B bus
Store A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus
Stored B data to A bus
H = High voltage level
L
= Low voltage level
X = Don't care
= Low-to-High clock transition
*
The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are always
enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.
**
If both Select controls (SAB and SBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must be
staggered in order to load both registers.
LOGIC DIAGRAM
1D
C1
Q
19
18
17
16
15
14
13
B1
B2
B3
B4
B5
B6
B7
5
6
7
8
9
10
11
A1
A2
A3
A4
A5
A6
A7
DETAIL A X 7
OEBA
OEAB
CPBA
SBA
CPAB
SAB
21
3
23
22
1
2
20
B0
1D
C1
Q
4
A0
1of 8 Channels
SA00098
Philips Semiconductors
Product specification
74ABT651
Octal transceiver/register, inverting (3-State)
1995 Sep 06
4
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +7.0
V
I
IK
DC input diode current
V
I
< 0
18
mA
V
I
DC input voltage
3
1.2 to +7.0
V
I
OK
DC output diode current
V
O
< 0
50
mA
V
OUT
DC output voltage
3
output in Off or High state
0.5 to +5.5
V
I
OUT
DC output current
output in Low state
128
mA
T
stg
Storage temperature range
65 to 150
C
NOTES:
1. 1Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
Min
Max
UNIT
V
CC
DC supply voltage
4.5
5.5
V
V
I
Input voltage
0
V
CC
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level Input voltage
0.8
V
I
OH
High-level output current
32
mA
I
OL
Low-level output current
64
mA
t/
v
Input transition rise or fall rate
0
10
ns/V
T
amb
Operating free-air temperature range
40
+85
C
Philips Semiconductors
Product specification
74ABT651
Octal transceiver/register, inverting (3-State)
1995 Sep 06
5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
C
T
amb
= 40
C
to +85
C
UNIT
Min
Typ
Max
Min
Max
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= 18mA
0.9
1.2
1.2
V
V
CC
= 4.5V; I
OH
= 3mA; V
I
= V
IL
or V
IH
2.5
3.2
2.5
V
V
OH
Highlevel output voltage
V
CC
= 5.0V; I
OH
= 3mA; V
I
= V
IL
or V
IH
3.0
3.7
3.0
V
V
CC
= 4.5V; I
OH
= 32mA; V
I
= V
IL
or V
IH
2.0
2.30
2.0
V
V
OL
Lowlevel output voltage
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
0.42
0.55
0.55
V
V
RST
3
Power-up output low voltage
V
CC
= 5.5V; I
O
= 1mA; V
I
= GND or V
CC
0.13
0.55
0.55
V
I
I
Input leakage
Control pins
V
CC
= 5.5V; V
I
= GND or 5.5V
0.01
1.0
1.0
A
I
I
Input leakage
current
Data pins
V
CC
= 5.5V; V
I
= GND or 5.5V
5
100
100
A
I
OFF
Power-off leakage current
V
CC
= 0.0V; V
O
or V
I
4.5V
5.0
100
100
A
I
PU
/I
PD
Power-up/down 3-State
output current
4
V
CC
= 2.1V; V
O
= 0.5V; V
OE
= Don't Care;
V
I
= GND or V
CC
5.0
50
50
A
I
IH
+ I
OZH
3State output High current
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
5.0
50
50
A
I
IL
+ I
OZL
3State output Low current
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
5.0
50
50
A
I
CEX
Output High leakage current
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
5.0
50
50
A
I
O
Output current
1
V
CC
= 5.5V; V
O
= 2.5V
40
65
180
40
180
mA
I
CCH
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
110
250
250
A
I
CCL
Q i
l
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
20
30
30
mA
I
CCZ
Quiescent supply current
V
CC
= 5.5V; Outputs 3State;
V
I
= GND or V
CC
110
250
250
A
I
CC
Additional supply current per
input pin
2
V
CC
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND; V
CC
= 5.5V
0.3
1.5
1.5
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0V and 2.1V, with a transition time of up to 10msec. From V
CC
= 2.1V to V
CC
= 5V
10%, a
transition time of up to 100
sec is permitted.
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
T
amb
= -40 to
+85
o
C
V
CC
= +5.0V
0.5V
UNIT
Min
Typ
Max
Min
Max
f
MAX
Maximum clock frequency
1
125
300
125
MHz
t
PLH
t
PHL
Propagation delay
CPAB to Bn or CPBA to An
1
2.2
1.7
3.8
4.4
5.1
5.1
2.2
1.7
5.6
5.6
ns
t
PLH
t
PHL
Propagation delay
An to Bn or Bn to An
2
1.5
1.5
3.2
3.7
5.1
4.6
1.5
1.5
6.2
5.4
ns
t
PLH
t
PHL
Propagation delay
SAB to Bn or SBA to An
3
1.5
1.5
3.8
4.4
5.1
4.9
1.5
1.5
6.5
5.9
ns
t
PZH
t
PZL
Output enable time
OEBA to An
5
6
1.3
2.5
3.7
4.7
4.6
6.8
1.3
2.5
5.8
8.5
ns
t
PHZ
t
PLZ
Output disable time
OEBA to An
5
6
1.5
1.5
4.0
3.2
4.5
3.8
1.5
1.5
5.0
4.1
ns
t
PZH
t
PZL
Output enable time
OEAB to Bn
5
6
1.8
2.9
3.4
4.5
6.1
6.5
1.8
2.9
6.5
7.4
ns
t
PHZ
t
PLZ
Output disable time
OEAB to Bn
5
6
1.5
1.5
3.8
3.1
4.5
4.4
1.5
1.5
5.5
5.1
ns