ChipFind - документация

Электронный компонент: 74ABT74D

Скачать:  PDF   ZIP
Philips Semiconductors
Product specification
74ABT74
Dual D-type flip-flop
1
853-1813 15793
1995 Sep 22
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
C;
GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation
delay
CPn to
Qn, Qn
C
L
= 50pF;
V
CC
= 5V
3.0
2.5
ns
t
OSLH
t
OSHL
Output to
Output skew
CC
0.5
ns
C
IN
Input
capacitance
V
I
= 0V or V
CC
3
pF
I
CC
Total supply
current
Outputs disabled;
V
CC
= 5.5V
50
A
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
V
CC
SD1
Q1
Q1
CP1
RD1
D1
RD1
D0
Q0
CP0
SD1
Q0
SF00045
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1, 2, 3, 4, 10,
11, 12, 13
RDn, Dn,
CPn, SDn
Data inputs
5, 6, 8, 9
Qn, Qn
Data outputs
7
GND
Ground (0V)
14
V
CC
Positive supply voltage
LOGIC SYMBOL
Q0 Q0 Q1 Q1
5
6
9
8
V
CC
= Pin 14
GND = Pin 7
3
4
1
11
10
13
CP0
SD0
RD0
CP1
SD1
RD1
D0
D1
2
12
SA00359
DESCRIPTION
The 74ABT74 is a dual positive edge-triggered D-type flip-flop
featuring individual data, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active low inputs and operate independently of the clock input.
When set and reset are inactive (high), data at the D input is
transferred to the Q and Q outputs on the low-to-high transition of
the clock. Data must be stable just one setup time prior to the
low-to-high transition of the clock for predictable operation. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. Following the hold time
interval, data at the D input may be changed without affecting the
levels of the output.
LOGIC SYMBOL (IEEE/IEC)
4
3
2
1
10
11
12
13
5
6
9
8
&
S
S
C1
C2
R
1D
2D
R
SF00047
LOGIC DIAGRAM
V
CC
= Pin 14
GND = Pin 7
5, 9
6, 8
Q
Q
4, 10
1, 13
3, 11
2, 12
SD
RD
CP
D
SF00048
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
14-Pin Plastic DIP
40
C to +85
C
74ABT74 N
74ABT74 N
SOT27-1
14-Pin plastic SO
40
C to +85
C
74ABT74 D
74ABT74 D
SOT108-1
14-Pin Plastic SSOP Type II
40
C to +85
C
74ABT74 DB
74ABT74 DB
SOT337-1
14-Pin Plastic TSSOP Type I
40
C to +85
C
74ABT74 PW
74ABT74PW DH
SOT402-1
Philips Semiconductors
Product specification
74ABT74
Dual D-type flip-flop
1995 Sep 22
2
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
SD
RD
CP
D
Q
Q
OPERATING
MODE
L
H
X
X
H
L
Asynchronous set
H
L
X
X
L
H
Asynchronous
reset
L
L
X
X
H
H
Undetermined*
H
H
h
H
L
Load "1"
H
H
l
L
H
Load "0"
H
H
X
NC
NC
Hold
NOTES:
H = High voltage level
h
= High voltage level one setup time prior to low-to-high
clock transition
L
= Low voltage level
l
= Low voltage level one setup time prior to low-to-high
clock transition
NC= No change from the previous setup
X = Don't care
= Low-to-high clock transition
= Not low-to-high clock transition
*
= This setup is unstable and will change when either set
or reset return to the high level.
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +7.0
V
I
IK
DC input diode current
V
I
< 0
18
mA
V
I
DC input voltage
3
1.2 to +7.0
V
I
OK
DC output diode current
V
O
< 0
50
mA
V
OUT
DC output voltage
3
output in Off or High state
0.5 to +5.5
V
I
OUT
DC output current
output in Low state
40
mA
T
stg
Storage temperature range
65 to 150
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
MAX
UNIT
V
CC
DC supply voltage
4.5
5.5
V
V
I
Input voltage
0
V
CC
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
I
OH
High-level output current
15
mA
I
OL
Low-level output current
20
mA
t/
v
Input transition rise or fall rate
0
10
ns/V
T
amb
Operating free-air temperature range
40
+85
C
Philips Semiconductors
Product specification
74ABT74
Dual D-type flip-flop
1995 Sep 22
3
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
C
T
amb
= 40
C
to +85
C
UNIT
MIN
TYP
MAX
MIN
MAX
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= 18mA
0.9
1.2
1.2
V
V
OH
High-level output voltage
V
CC
= 4.5V; I
OH
= 15mA; V
I
= V
IL
or V
IH
2.5
2.9
2.5
V
V
OL
Low-level output voltage
V
CC
= 4.5V; I
OL
= 20mA; V
I
= V
IL
or V
IH
0.35
0.5
0.5
V
I
I
Input leakage current
V
CC
= 5.5V; V
I
= GND or 5.5V
0.01
1.0
1.0
A
I
OFF
Power-off leakage current
V
CC
= 0.0V; V
O
or V
I
4.5V
5.0
100
100
A
I
CEX
Output High leakage current
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
5.0
50
50
A
I
O
Output current
1
V
CC
= 5.5V; V
O
= 2.5V
50
75
180
50
180
mA
I
CC
Quiescent supply current
V
CC
= 5.5V; V
I
= GND or V
CC
2
50
50
A
I
CC
Additional supply current per
input pin
2
V
CC
= 5.5V; One data input at 3.4V, other
inputs at V
CC
or GND
0.25
500
500
A
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flop or latch after applying the power.
AC ELECTRICAL CHARACTERISTICS
GND = 0V; t
R
= t
F
= 2.5ns; C
L
= 50pF, R
L
= 500
SYMBOL
PARAMETER
WAVEFORM
LIMITS
UNIT
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
C
V
CC
= +5.0V
T
amb
= 40
C to +85
C
V
CC
= +5.0V
0.5V
UNIT
MIN
TYP
MAX
MIN
MAX
f
MAX
Maximum clock frequency
1
180
250
150
MHz
t
PLH
t
PHL
Propagation delay
CPn to Qn, Qn
1
1.0
1.0
3.0
2.5
4.2
3.5
1.0
1.0
4.7
4.0
ns
t
PLH
t
PHL
Propagation delay
Sn, Rn to Qn, Qn
3
1.0
1.0
3.4
2.9
4.9
4.5
1.0
1.0
6.2
5.2
ns
t
OSHL
t
OSLH
1
Output to Output skew
An or Bn to Yn
4
0.5
0.6
0.6
ns
NOTE:
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same
device. The specification applies to any outputs switching in the the same direction, either HIGHto-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
);
parameter guaranteed by design.
AC SETUP REQUIREMENTS
GND = 0V; t
R
= t
F
= 2.5ns; C
L
= 50pF, R
L
= 500
SYMBOL
PARAMETER
WAVEFORM
LIMITS
UNIT
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
C
V
CC
= +5.0V
T
amb
= 40
C to +85
C
V
CC
= +5.0V
0.5V
UNIT
MIN
TYP
MIN
t
su
(H)
t
su
(L)
Setup time, high or low
Dn to CPn
1
2.6
2.4
1.4
1.4
2.6
2.4
ns
t
h
(H)
t
h
(L)
Hold time, high or low
Dn to CPn
1
0
0
1.4
1.4
0
0
ns
t
w
(H)
t
w
(L)
CPn pulse width,
high or low
1
1.7
1.7
1.0
1.0
2.1
2.1
ns
t
w
(L)
SDn, RDn pulse width, low
3
2.0
1.3
2.2
ns
t
rec
Recovery time
SDn, RDn to CPn
2
2.1
1.4
2.4
ns
Philips Semiconductors
Product specification
74ABT74
Dual D-type flip-flop
1995 Sep 22
4
AC WAVEFORMS
V
M
= 1.5V, V
IN
= GND to 3.0V
The shaded areas indicate when the input is permitted to change for predictable output performance
VM
VM
CPn
VM
VM
VM
VM
VM
VM
tsu(H)
th(H)
Dn
Qn
VM
tw(H)
1/fmax
tsu(L)
th(L)
VM
VM
tPLH
Qn
tw(L)
tPHL
tPHL
tPLH
SF00049
Waveform 1.
Propagation delay for data to output,
data setup time and hold times, and clock width,
and maximum clock frequency
SDn or RDn
VM
VM
trec
CPn
SF00051
Waveform 2.
Recovery time for set or reset to clock
VM
VM
RDn
VM
Qn
VM
VM
VM
tPLH
Qn
tw(L)
tPHL
tPHL
tPLH
SDn
VM
VM
tw(L)
SF00050
Waveform 3.
Propagation delay for set and reset to output,
set and reset pulse width
OUTPUT N
same part
INPUT
SA00381
OUTPUT
t
PLH
MIN
t
PHL
MIN
t
PLH
MAX
t
PHL
MAX
t
OSLH
t
OSHL
Waveform 4. Common edge skew
Philips Semiconductors
Product specification
74ABT74
Dual D-type flip-flop
1995 Sep 22
5
TEST CIRCUIT AND WAVEFORMS
PULSE
GENERATOR
RT
VIN
D.U.T.
VOUT
CL
RL
VCC
Test Circuit for Outputs
VM
VM
tW
AMP (V)
NEGATIVE
PULSE
10%
10%
90%
90%
0V
VM
VM
tW
AMP (V)
POSITIVE
PULSE
90%
90%
10%
10%
0V
tTHL (tF)
tTLH (tR)
tTHL (tF)
tTLH (tR)
V
M
= 1.5V
Input Pulse Definition
DEFINITIONS
R
L
=
Load resistor; see AC CHARACTERISTICS for value.
C
L
=
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
R
T
=
Termination resistance should be equal to Z
OUT
of
pulse generators.
INPUT PULSE REQUIREMENTS
FAMILY
74ABT
SH00067
Amplitude
Rep. Rate
t
W
t
F
3.0V
1MHz
500ns
2.5ns
t
R
2.5ns