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Электронный компонент: 74ABT833

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Philips
Semiconductors
74ABT833
Octal transceiver with parity
generator/checker (3-State)
Product specification
1993 Jun 21
INTEGRATED CIRCUITS
IC23 Data Handbook
Philips Semiconductors
Product specification
74ABT833
Octal transceiver with parity generator/checker
(3-State)
2
1993 Jun 21
8531619 10087
FEATURES
Low static and dynamic power dissipation with high speed and
high output drive
Open-collector ERROR output with flag register
Output capability: +64mA/32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200 V per Machine Model
Power up/down 3-State
Live insertion/extraction permitted
DESCRIPTION
The 74ABT833 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT833 is an octal transceiver with a parity
generator/checker and is intended for bus-oriented applications.
When Output Enable A (OEA) is High, it will place the A outputs in a
high impedance state. Output Enable B (OEB) controls the B
outputs in the same way.
The parity generator creates an odd parity output (PARITY) when
OEB is Low. When OEA is Low, the parity of the B port, including
the PARITY input, is checked for odd parity. When an error is
detected, the error data is sent to the input of a storage register. If a
Low-to-High transition happens at the clock input (CP), the error
data is stored in the register and the Open-collector error flag
(ERROR) will go Low. The error flag register is cleared with a Low
pulse on the CLEAR input.
If both OEA and OEB are Low, data will flow from the A bus to the B
bus and the part is forced into an error condition which creates an
inverted PARITY output. This error condition can be used by the
designer for system diagnostics.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
An to Bn or Bn to An
C
L
= 50pF; V
CC
= 5V
3.4
ns
t
PLH
t
PHL
Propagation delay
An to PARITY
C
L
= 50pF; V
CC
= 5V
7.4
ns
C
IN
Input capacitance
V
I
= 0V or V
CC
4
pF
C
I/O
I/O capacitance
Outputs disabled;
V
O
= 0V or V
CC
7
pF
I
CCZ
Total supply current
Outputs disabled; V
CC
=5.5V
50
A
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
24-Pin Plastic DIP
40
C to +85
C
74ABT833 N
74ABT833 N
SOT222-1
24-Pin plastic SO
40
C to +85
C
74ABT833 D
74ABT833 D
SOT137-1
24-Pin Plastic SSOP Type II
40
C to +85
C
74ABT833 DB
74ABT833 DB
SOT340-1
24-Pin Plastic TSSOP Type I
40
C to +85
C
74ABT833 PW
74ABT833PW DH
SOT355-1
PIN CONFIGURATION
24
23
22
21
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
VCC
GND
CLEAR
OEA
B0
B1
B2
B3
B6
B7
PARITY
OEB
A0
A1
A2
A3
A4
A5
A6
A7
ERROR
CP
B4
B5
TOP VIEW
SA00212
PIN DESCRIPTION
SYMBOL
PIN NUMBER
NAME AND FUNCTION
A0 A7
2, 3, 4, 5,
6, 7, 8, 9
A port 3-State inputs/outputs
B0 B7
23, 22, 21, 20,
19, 18, 17, 16
B port 3-State inputs/outputs
OEA
1
Enables the A outputs when
Low
OEB
14
Enables the B outputs when
Low
PARITY
15
Parity output/input
ERROR
10
Error output (open collector)
CLEAR
11
Clears the error flag register
when Low
CP
13
Clock input
GND
12
Ground (0V)
V
CC
24
Positive supply voltage
Philips Semiconductors
Product specification
74ABT833
Octal transceiver with parity generator/checker
(3-State)
1993 Jun 21
3
LOGIC SYMBOL
OEB
OEA
CLEAR
14
1
11
15
10
PARITY
ERROR
CP
13
2
3
4
5
6
7
8
9
A0 A1 A2 A3 A4 A5 A6 A7
B0 B1 B2 B3 B4 B5 B6 B7
23 22 21 20 19 18 17 16
SA00213
FUNCTION TABLE
INPUTS
OUTPUTS
MODE
OEB
OEA
An
of Highs
Bn + Parity
of Highs
An
Bn
PARITY
A data to B bus and generate odd parity
output
L
H
Odd
Even
(output)
(input)
An
L
H
B data to A bus and check for parity error
1
H
L
(output)
X
Bn
(input)
(input)
A bus and B bus disabled
2
H
H
X
X
Z
Z
Z
A data to B bus and generate inverted
parity output
L
L
Odd
Even
(output)
(input)
An
H
L
NOTES:
1. Error checking is detailed in the Error Flag Function Table below.
2. When clocked, the error output is Low if the sum of A inputs is even or High if the sum of A inputs is odd.
ERROR FLAG FUNCTION TABLE
INPUTS
Internal node
Output
MODE
CLEAR
CP
Bn + Parity
of Highs
Point "P"
Prestate
ERRORn1
ERROR
OUTPUT
Sample
H
H
H
X
Odd
Even
X
H
L
X
H
X
L
H
L
L
Hold
H
X
X
X
NC
Clear
L
X
X
X
X
H
H
= High voltage level steady state
L
= Low voltage level steady state
X
= Don't care
NC = No change
Z
= High impedance "off" state
= Low-to-High clock transition
= Not a Low-to-High clock transition
Philips Semiconductors
Product specification
74ABT833
Octal transceiver with parity generator/checker
(3-State)
1993 Jun 21
4
LOGIC DIAGRAM
8
8
8
8
8
MUX
Sel A/B
}
A
}
B
9
9bit
Odd
Parity
Tree
"P"
D
R
A0 A7
OEB
OEA
CP
CLEAR
B0 B7
PARITY
ERROR
SA00214
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +7.0
V
I
IK
DC input diode current
V
I
< 0
18
mA
V
I
DC input voltage
3
1.2 to +7.0
V
I
OK
DC output diode current
V
O
< 0
50
mA
V
OUT
DC output voltage
3
output in Off or High state
0.5 to +5.5
V
I
OUT
DC output current
output in Low state
128
mA
T
stg
Storage temperature range
65 to 150
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors
Product specification
74ABT833
Octal transceiver with parity generator/checker
(3-State)
1993 Jun 21
5
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
Max
V
CC
DC supply voltage
4.5
5.5
V
V
I
Input voltage
0
V
CC
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
V
OH
High-level output voltage, ERROR
5.5
V
I
OH
High-level output current
32
mA
I
OL
Low-level output current
64
mA
t/
v
Input transition rise or fall rate
0
5
ns/V
T
amb
Operating free-air temperature range
40
+85
C
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
C
T
amb
= 40
C
to +85
C
UNIT
Min
Typ
Max
Min
Max
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= 18mA
0.9
1.2
1.2
V
I
OH
High-level output current
ERROR ONLY
V
CC
= 5.5V; V
OH
= 5.5V; V
I
= V
IL
or V
IH
20
20
A
V
CC
= 4.5V; I
OH
= 3mA; V
I
= V
IL
or V
IH
2.5
3.5
2.5
V
V
OH
High-level output voltage
All outputs except ERROR
V
CC
= 5.0V; I
OH
= 3mA; V
I
= V
IL
or V
IH
3.0
4.0
3.0
V
V
CC
= 4.5V; I
OH
= 32mA; V
I
= V
IL
or V
IH
2.0
2.6
2.0
V
V
OL
Low-level output voltage
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
0.42
0.55
0.55
V
I
I
Input leakage
Control pins
V
CC
= 5.5V; V
I
= GND or 5.5V
0.01
1.0
1.0
A
current
Data pins
V
CC
= 5.5V; V
I
= GND or 5.5V
5
100
100
A
I
OFF
Power-off leakage current
V
CC
= 0.0V; V
I
or V
O
4.5V
5.0
100
100
V
I
PU
I
PD
Power-up/down 3-State
output current
3
V
CC
= 2.0V; or V
O
= 0.5V; V
I
= GND or V
CC
;
V
OE
= Don't care
5.0
50
50
V
I
IH
+ I
OZH
3-State output High current
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
5.0
50
50
A
I
IL
+ I
OZL
3-State output Low current
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
5.0
50
50
A
I
CEX
Output High leakage current
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
5.0
50
50
A
I
O
Output current
1
V
CC
= 5.5V; V
O
= 2.5V
50
80
180
50
180
mA
I
CCH
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
50
250
250
A
I
CCL
Quiescent supply current
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
20
30
30
mA
I
CCZ
V
CC
= 5.5V; Outputs 3-State;
V
I
= GND or V
CC
50
250
250
A
I
CC
Additional supply current per
input pin
2
V
CC
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
0.3
1.5
1.5
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. This parameter is valid for any V
CC
between 0V and 2.1, with a transition time of up to 10msec. From V
CC
= 2.1V to V
CC
= 5V
10%, a
transition of up to 100
sec is permitted. The ERROR output pin 10 is not included in this spec due to the open collector design.