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Электронный компонент: 74ABT845D

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Philips Semiconductors
Product specification
74ABT845
8-bit bus interface latch with set and reset
(3-State)
1
1995 Sep 06
853-1703 15702
FEATURES
High speed parallel latches
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Broadside pinout
Output capability: +64mA/32mA
Power-up 3-State
Power-up reset
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT845 consists of eight D-type latches with 3-State outputs.
In addition to the LE, OE, MR and PRE pins, the 74ABT845 has two
additional OE pins, making a total of three Output Enable (OE0,
OE1, OE2) pins. The multiple Output enables allow multiuser control
of the interface, e.g., CS, DMA, and RD/WR.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
Dn to Qn
C
L
= 50pF; V
CC
= 5V
5.4
ns
C
IN
Input capacitance
V
I
= 0V or V
CC
4
pF
C
OUT
Output capacitance
Outputs disabled;
V
O
= 0V or V
CC
7
pF
I
CCZ
Total supply current
Outputs disabled; V
CC
= 5.5V
500
nA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
24-Pin Plastic DIP
40
C to +85
C
74ABT845 N
74ABT845 N
SOT222-1
24-Pin plastic SO
40
C to +85
C
74ABT845 D
74ABT845 D
SOT137-1
24-Pin Plastic SSOP Type II
40
C to +85
C
74ABT845 DB
74ABT845 DB
SOT340-1
24-Pin Plastic TSSOP Type I
40
C to +85
C
74ABT845 PW
74ABT845PW DH
SOT355-1
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
15
16
17
18
19
20
21
22
23
24
OE0
OE1
D0
D1
D2
D3
D4
D5
D6
Q6
D7
Q5
Q4
Q3
Q2
Q1
Q0
OE2
VCC
Q7
11
14
MR
PRE
12
13
GND
LE
TOP VIEW
SA00258
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1, 2, 23
OE0 OE2
Output enable inputs
(active-Low)
3, 4, 5, 6,
7, 8, 9, 10
D0-D7
Data inputs
22, 21, 20, 19,18,
17, 16, 15
Q0-Q7
Data outputs
11
MR
Master reset input (active-Low)
13
LE
Latch enable input
(active-High)
14
PRE
Preset input (active-Low)
12
GND
Ground (0V)
24
V
CC
Positive supply voltage
Philips Semiconductors
Product specification
74ABT845
8-bit bus interface latch with set and reset
(3-State)
1995 Sep 06
2
LOGIC SYMBOL (IEEE/IEC)
3
4
5
6
7
8
9
C1
13
R
11
10
S2
14
23
EN
2
1
&
2
1D
22
21
20
19
18
17
16
15
SA00260
LOGIC SYMBOL
13
14
LE
PRE
11
1
MR
OE0
2
OE1
23
OE2
3
4
5
6
7
8
9
10
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
22 21 20 19 18 17 16 15
SA00259
FUNCTION TABLE
INPUTS
OUTPU
TS
OPERATING
MODE
OE
n
PR
E
MR
LE
Dn
Qn
L
L
X
X
X
H
Preset
L
H
L
X
X
L
Clear
L
L
H
H
H
H
H
H
L
H
L
H
Transparent
L
L
H
H
H
H
l
h
L
H
Latched
H
X
X
X
X
Z
High impedance
L
H
H
L
X
NC
Hold
H = High voltage level
h
= High voltage level one set-up time prior to the High-to-Low LE
transition
L
= Low voltage level
l
= Low voltage level one set-up time prior to the High-to-Low LE
transition
NC= No change
X = Don't care
Z = High impedance "off" state
= High-to-Low transition
LOGIC DIAGRAM
13
LE
2
OE1
L
Q
D
3
D0
Q0
22
L
Q
D
4
D1
Q1
21
L
Q
D
5
D2
Q2
20
L
Q
D
6
D3
Q3
19
L
Q
D
7
D4
Q4
18
L
Q
D
8
D5
Q5
17
L
Q
D
9
D6
Q6
16
L
Q
D
10
D7
Q7
P
P
P
P
P
P
P
P
15
C
C
C
C
C
C
C
C
11
MR
14
PRE
OE0
OE2
1
23
SA00261
Philips Semiconductors
Product specification
74ABT845
8-bit bus interface latch with set and reset
(3-State)
1995 Sep 06
3
ABSOLUTE MAXIMUM RATINGS
1,2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +7.0
V
I
IK
DC input diode current
V
I
< 0
18
mA
V
I
DC input voltage
3
1.2 to +7.0
V
I
OK
DC output diode current
V
O
< 0
50
mA
V
OUT
DC output voltage
3
output in Off or High state
0.5 to +5.5
V
I
OUT
DC output current
output in Low state
128
mA
T
stg
Storage temperature range
65 to 150
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
Max
V
CC
DC supply voltage
4.5
5.5
V
V
I
Input voltage
0
V
CC
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
I
OH
High-level output current
32
mA
I
OL
Low-level output current
64
mA
t/
v
Input transition rise or fall rate
0
5
ns/V
T
amb
Operating free-air temperature range
40
+85
C
Philips Semiconductors
Product specification
74ABT845
8-bit bus interface latch with set and reset
(3-State)
1995 Sep 06
4
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
C
T
amb
= 40
C
to +85
C
UNIT
Min
Typ
Max
Min
Max
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= 18mA
0.9
1.2
1.2
V
V
CC
= 4.5V; I
OH
= 3mA; V
I
= V
IL
or V
IH
2.5
2.9
2.5
V
V
OH
Highlevel output voltage
V
CC
= 5.0V; I
OH
= 3mA; V
I
= V
IL
or V
IH
3.0
3.4
3.0
V
V
CC
= 4.5V; I
OH
= 32mA; V
I
= V
IL
or V
IH
2.0
2.4
2.0
V
V
OL
Lowlevel output voltage
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
0.42
0.55
0.55
V
V
RST
Power-up output low
voltage
3
V
CC
= 5.5V; I
O
= 1mA; V
I
= GND or V
CC
0.13
0.55
0.55
V
I
I
Input leakage current
V
CC
= 5.5V; V
I
= GND or 5.5V
0.01
1.0
1.0
A
I
OFF
Power-off leakage current
V
CC
= 0.0V; V
O
or V
I
4.5V
5.0
100
100
A
I
PU/PD
Power-up/down
3-state output current
4
V
CC
= 2.1V; V
O
= 0.5V; V
OE
= V
CC;
V
I
= GND or V
CC
5.0
50
50
A
I
OZH
3-State output High current
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
5.0
50
50
A
I
OZL
3-State output Low current
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
5.0
50
50
A
I
CEX
Output High leakage current
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
5.0
50
50
A
I
O
Output current
1
V
CC
= 5.5V; V
O
= 2.5V
50
80
180
50
180
mA
I
CCH
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
0.5
250
250
A
I
CCL
Quiescent supply current
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
24
30
30
mA
I
CCZ
V
CC
= 5.5V; Outputs 3-State;
V
I
= GND or V
CC
0.5
250
250
A
I
CC
Additional supply current per
input pin
2
V
CC
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
0.5
1.5
1.5
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0V and 2.1V with a transition time of up to 10msec. For V
CC
= 2.1V to V
CC
= 5V
"
10%, a
transition time of up to 100
sec is permitted.
Philips Semiconductors
Product specification
74ABT845
8-bit bus interface latch with set and reset
(3-State)
1995 Sep 06
5
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
T
amb
= -40 to
+85
o
C
V
CC
= +5.0V
0.5V
UNIT
Min
Typ
Max
Min
Max
t
PLH
t
PHL
Propagation delay
Dn to Qn
1
1.0
2.2
3.9
5.4
5.4
6.8
1.0
2.2
6.2
7.8
ns
t
PLH
t
PHL
Propagation delay
LE to Qn
2
2.0
2.8
5.1
6.4
6.6
7.9
2.0
2.8
7.5
8.9
ns
t
PLH
t
PHL
Propagation delay
PRE to Qn
1
2.2
3.0
4.9
5.3
6.6
6.8
2.2
3.0
7.8
7.4
ns
t
PLH
t
PHL
Propagation delay
MR to Qn
1
2.4
3.1
4.9
5.9
6.4
7.3
2.4
3.1
7.3
8.5
ns
t
PZH
t
PZL
Output enable time
OEn to Qn
4
5
1.0
2.0
3.8
4.7
5.4
6.1
1.0
2.0
6.3
6.7
ns
t
PHZ
t
PLZ
Output disable time
OEn to Qn
4
5
1.9
2.2
4.6
4.7
6.2
6.4
1.9
2.2
7.2
7.0
ns
AC SETUP REQUIREMENTS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
T
amb
= -40 to +85
o
C
V
CC
= +5.0V
0.5V
UNIT
Min
Typ
Min
t
s
(H)
t
s
(L)
Setup time, High or Low
Dn to LE
3
2.8
3.5
1.0
1.4
2.8
3.5
ns
t
h
(H)
t
h
(L)
Hold time, High or Low
Dn to LE
3
1.0
1.0
1.2
0.6
1.0
1.0
ns
t
w
(H)
LE pulse width, High
3
3.0
1.5
3.0
ns
t
w
(L)
PRE pulse width, Low
6
3.5
2.0
3.5
ns
t
w
(L)
MR pulse width, Low
6
2.8
1.3
2.8
ns
t
rec
PRE recovery time
6
3.0
1.4
3.0
ns
t
rec
MR recovery time
6
3.4
1.6
3.4
ns