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Электронный компонент: 74ABTH16823A

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Philips
Semiconductors
74ABT16823A
74ABTH16823A
18-bit bus interface D-type flip-flop
with reset and enable (3-State)
Product specification
Supersedes data of 1995 Sep 28
IC23 Data Handbook
1998 Feb 27
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74ABT16823A
74ABTH16823A
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
2
1998 Feb 27
853-1791 19025
FEATURES
Two sets of high speed parallel registers with positive
edge-triggered D-type flip-flops
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Live insertion/extraction permitted
Power-up 3-State
74ABTH16823A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
Power-up Reset
Output capability: +64mA/32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT16823A 18-bit bus interface register is designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of buses
carrying parity.
The 74ABT16823A has two 9-bit wide buffered registers with Clock
Enable (nCE) and Master Reset (nMR) which are ideal for parity bus
interfacing in high microprogrammed systems.
The registers are fully edge-triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop's Q output.
Two options are available, 74ABT16823A which does not have the
bus-hold feature and 74ABTH16823A which incorporates the
bus-hold feature.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
nCP to nQx
C
L
= 50pF; V
CC
= 5V
2.3
1.9
ns
C
IN
Input capacitance
V
I
= 0V or V
CC
4
pF
C
OUT
Output capacitance
V
O
= 0V or V
CC
; 3-State
6
pF
I
CCZ
Quiescent supply current
Outputs disabled; V
CC
= 5.5V
500
A
I
CCL
Quiescent su
ly current
Outputs low; V
CC
= 5.5V
9
mA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
40
C to +85
C
74ABT16823A DL
BT16823A DL
SOT371-1
56-Pin Plastic TSSOP Type II
40
C to +85
C
74ABT16823A DGG
BT16823A DGG
SOT364-1
56-Pin Plastic SSOP Type III
40
C to +85
C
74ABTH16823A DL
BH16823A DL
SOT371-1
56-Pin Plastic TSSOP Type II
40
C to +85
C
74ABTH16823A DGG
BH16823A DGG
SOT364-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
2, 27
1OE, 2OE
Output enable input (active-Low)
54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31
1D0-1D8
2D0-2D8
Data inputs
3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26
1Q0-1Q8
2Q0-2Q8
Data outputs
56, 29
1CP, 2CP
Clock pulse input (active rising edge)
55, 30
1CE, 2CE
Clock enable input (active-Low)
1, 28
1MR, 2MR
Master reset input (active-Low)
4, 11, 18, 25, 32, 39, 46, 53
GND
Ground (0V)
7, 22, 35, 50
V
CC
Positive supply voltage
Philips Semiconductors
Product specification
74ABT16823A
74ABTH16823A
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
1998 Feb 27
3
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1MR
1OE
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
GND
V
CC
GND
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
GND
2Q3
2Q4
2Q5
V
CC
2Q6
2Q7
GND
2Q8
2OE
2MR
1CP
1CE
1D0
GND
1D1
1D2
V
CC
1D3
1D4
1D5
GND
1D6
1D7
1D8
2D0
2D1
2D2
GND
2D3
2D4
2D5
V
CC
2D6
2D7
GND
2D8
2CE
2CP
SH00014
LOGIC SYMBOL (IEEE/IEC)
EN1
1, 2
5, 6
SH00015
1
28
30
29
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
25
4D
8D
2
56
55
27
R2
G3
3C4
EN5
R6
G7
7C8
1MR
1OE
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2OE
2MR
1CP
1CE
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2CE
2CP
Philips Semiconductors
Product specification
74ABT16823A
74ABTH16823A
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
1998 Feb 27
4
LOGIC DIAGRAM
R
nD
nD0
nQ0
nMR
nOE
R
nD
nD1
nQ1
R
nD
nD2
nQ2
R
nD
nD3
nQ3
R
nD
nD4
nQ4
R
nD
nD5
nQ5
R
nD
nD6
nQ6
R
nD
nD7
nQ7
R
nD
nD8
nQ8
nCP
nCE
SH00016
CP
CP
CP
CP
CP
CP
CP
CP
CP
Q
Q
Q
Q
Q
Q
Q
Q
Q
n = 1 or 2
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
nOE
nMR
nCE
nCP
nDx
nQ0 nQ8
OPERATING MODE
L
L
X
X
X
L
Clear
L
H
L
h
H
Load and read data
L
H
L
l
L
Load and read data
L
H
H
X
NC
Hold
H
X
X
X
X
Z
High impedance
H = High voltage level
h
= High voltage level one set-up time prior to the Low-to-High clock transition
L
= Low voltage level
l
= Low voltage level one set-up time prior to the Low-to-High clock transition
NC= No change
X = Don't care
Z = High impedance "off" state
= Low to High clock transition
= Not a Low-to-High clock transition
Philips Semiconductors
Product specification
74ABT16823A
74ABTH16823A
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
1998 Feb 27
5
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +7.0
V
I
IK
DC input diode current
V
I
< 0
18
mA
V
I
DC input voltage
3
1.2 to +7.0
V
I
OK
DC output diode current
V
O
< 0
50
mA
V
OUT
DC output voltage
3
output in Off or High state
0.5 to +5.5
V
I
O
DC output current
output in Low state
128
mA
I
OUT
DC output current
output in High state
64
mA
T
stg
Storage temperature range
65 to 150
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
MAX
UNIT
V
CC
DC supply voltage
4.5
5.5
V
V
I
Input voltage
0
V
CC
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
I
OH
High-level output current
32
mA
I
OL
Low-level output current
64
mA
t/
v
Input transition rise or fall rate
0
10
ns/V
T
amb
Operating free-air temperature range
40
+85
C