Philips Semiconductors
Product specification
74ABTL3205
10-bit BTL transceiver with registers
2
1995 Jun 16
853-1802 15352
FEATURES
10-bit BTL transceiver
Drives heavily loaded backplanes with equivalent load
impedances down to 10 ohms
High drive 100mA BTL open collector drivers on B-port
Allows incident wave switching in heavily loaded backplane buses
Reduced BTL voltage swing produces less noise and reduces
power consumption
Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
Compatible with IEEE Futurebus+ or proprietary BTL backplanes
Controlled output ramp and multiple GND pins minimize ground
bounce
Tight output skew (0.5nsec typical)
Glitch-free power up/down operation
Low I
CC
current
Supports live insertion
High density packaging
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
This transceiver is a 10 bit bidirectional transceiver and is intended
to provide the electrical interface to a high performance wired-OR
bus.
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good margins by limiting
the switching threshold to a narrow region centered at 1.55V.
The B-port interfaces to "Backplane Transceiver Logic" (See the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1V p-p, between 1V and 2V) and
reduced capacitive loading (<6pF) by placing an internal series
diode on the drivers. BTL also provides incident wave switching, a
necessity for high performance backplanes.
To support live insertion, OEB is held Low during power on/off cycles
to insure glitch free B port drivers. Proper bias for B port drivers
during live insertion is provided by the BIAS V pin when at a 5V level
while V
CC
is Low. The BIAS V pin is a low current input which will
reverse bias the BTL driver series Schottky diode, and also bias the
B port output pins to a voltage between 1.62V and 2.1V. This bias
function is in accordance with IEEE BTL standard 1194.1. If live
insertion is not a requirement, the BIAS V pin should be tied to a
V
CC
pin.
The LOGIC GND and BUS GND pins are isolated inside the
package to minimize noise coupling between the BTL and TTL
sides. These pins should be tied to a common ground external to the
package. The LOGIC V
CC
and BUS V
CC
pins are also isolated
internally to minimize noise and may be externally decoupled
separately or simply tied together.
This transceiver function is intended to operate in a half-duplex
mode. Low current in standby mode is obtained by powering down
unused circuitry. Likewise, transmit circuitry is powered down when
in receive mode and receive circuitry is powered down while in
transmit mode.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
TYPICAL
UNIT
t
PLH
Propagation delay
3.3
ns
t
PHL
An to Bn
3.7
ns
t
PLH
Propagation delay
3.6
ns
t
PHL
Bn to An
3.5
ns
C
OB
Output capacitance (B0 - B8) only)
6
pF
I
OL
Output current (B0 - B8) only)
100
mA
Standby
1
I
CC
Supply current
An to Bn
7
mA
Bn to An
18
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
52-PIN PQFP
40
C to +85
C
74ABTL3205 BB
74ABTL3205 BB
SOT379-1
Philips Semiconductors
Product specification
74ABTL3205
10-bit BTL transceiver with registers
1995 Jun 16
3
PIN CONFIGURATION
49
50
51
52
1
2
3
4
5
6
7
14 15
16 17 18 19 20
27
28
29
30
31
32
33
46
47
48
34
35
36
37
38
39
21
22 23 24 25 26
8
9
10
11
12
13
43
44
45
40
41
42
A1
A3
A4
A5
A6
TTL Gnd
TTL GND
TTL GND
BUS GND
B0
B2
B3
B4
B5
B6
BUS GND
BUS GND
BUS GND
BUS GND
BUS GND
A7
BG V
CC
BG GND
CC
BUS GND
B7
A0
A2
AClk2
TTL GND
TTL GND
TTL
Gnd
AP
AR
Power Up
M/S
IEA
T
ransmode
V
B1
BClk2
AClk1
TTL
Gnd
CC
V
AClkin
BiasV
OEA1
OEA2
OEB
Mode
Recmode
CC
V
BClk1
SA00138
AFP
PIN DESCRIPTION
SYMBOL
FUNCTION
ASSERTION
I/O
LOGIC
OEA1
Output enable data receiver group 1
Low
Input
TTL
OEA2
Output enable data receiver group 2
Low
Input
TTL
OEB
Output enable data transmitter
Low
Input
TTL
IEA
Output enable clock and framepulse receiver
Low
Input
TTL
M/S
Master/Slave select:
L:
Master, enable clock transmitter
H:
Slave, disable clock transmitter
Input
TTL
Mode
Low:
Data through mode
High:
Registered data mode
Input
TTL
Power Up
Power up mode, held low during power up to
disable clock and data transmitters
Low
Input
TTL
Recmode
Enables receiver
High
Input
TTL
Tranmode
Enables transmitter
High
Input
TTL
AClk1
Clock or data path
I/O
TTL
AClkln
IEA = H
Input for busclock
IEA = L
Output for busclock
I/O
TTL
A0..A3
data group 1
I/O
TTL
AClk2
Clock or data path
I/O
TTL
AFPIn
Alternate data path
Output
TTL
APAR
Alternate data path
Input
TTL
A4..A7
data group 2
I/O
TTL
BClk1
Clock or data path
I/O
BTL
B0..B3
data group 1
I/O
BTL
BClk2
Clock or data path
I/O
BTL
B4..B7
data group 2
I/O
BTL
Philips Semiconductors
Product specification
74ABTL3205
10-bit BTL transceiver with registers
1995 Jun 16
5
FUNCTION TABLE
INPUTS
MODE
An
Bn
ACLK
in
ACLK
1
ACLK
2
BCLK
1
BCLK
2
OEA1
OEA2
OEB
APAR
IEA
M/S
MODE
REC
MODE
TRAN
MODE
POWER
UP
An to Bn
(REGISTERED)
I
O
X
X
X
X
H
H
L
X
H
X
H
L
H
H
(REGISTERED)
h
O
X
X
X
X
H
H
L
X
H
X
H
L
H
H
AN to Bn
(THROUGH)
L
O
X
X
X
X
X
H
H
L
X
X
X
L
L
H
H
(THROUGH)
H
O
X
X
X
X
X
H
H
L
X
X
X
L
L
H
H
B0-B3
to
A A
O
L
X
X
X
X
X
L
X
H
X
X
X
X
H
L
L
A0-A3
(THROUGH)
O
H
X
X
X
X
X
L
X
H
X
X
X
X
H
L
L
B4-B7
to
A A
O
L
X
X
X
X
X
X
L
H
X
X
X
X
H
L
L
A4-A7
(THROUGH)
O
H
X
X
X
X
X
X
L
H
X
X
X
X
H
L
L
ACLK1
to
X
X
X
L
X
O
X
H
X
X
X
X
L
X
X
H
H
to
BCLK1
X
X
X
H
X
O
X
H
X
X
X
X
L
X
X
H
H
ACLK2
to
X
X
X
X
L
X
O
X
H
H
X
X
L
L
X
H
H
to
BCLK2
X
X
X
X
H
X
O
X
H
H
X
X
L
L
X
H
H
BCLK1
to
X
X
X
O
X
L
X
L
X
X
X
X
X
X
H
L
X
to
ACLK1
X
X
X
O
X
H
X
L
X
X
X
X
X
X
H
L
X
BCLK2
to
X
X
X
X
O
X
L
X
L
X
X
X
X
X
H
L
X
to
ACLK2
X
X
X
X
O
X
H
X
L
X
X
X
X
X
H
L
X
APAR
to
X
X
X
X
X
X
X
X
L
I
X
H
H
X
H
H
to
BCLK2
X
X
X
X
X
X
X
X
L
h
X
H
H
X
H
H
BCLK2
to
X
X
X
X
X
X
L
X
X
X
X
L
X
X
H
L
X
to
AFPIn
X
X
X
X
X
X
H
X
X
X
X
L
X
X
H
L
X
BCLK1
to
X
X
O
X
X
L
X
H
H
L
O
L
H
H
L
H
H
to
ACLKin
X
X
O
X
X
H
X
H
H
L
O
L
H
H
L
H
H
O
OUTPUTS
MODE
An
Bn
ACLK
in
ACLK1
ACLK2
BCLK1
BCLK2
AF
Pin
An to Bn
(REGISTERED)
Input
H*
X
X
X
X
X
X
(REGISTERED)
Input
L
X
X
X
X
X
X
AN to Bn
(THROUGH)
Input
H*
X
X
X
X
X
X
(THROUGH)
Input
L
X
X
X
X
X
X
B0-B3
to
A A
H
Input
Input
X
X
X
X
X
A0-A3
(THROUGH)
L
Input
Input
X
X
X
X
X
B4-B7
to
A A
H
Input
Input
X
X
X
X
X
A4-A7
(THROUGH)
L
Input
Input
X
X
X
X
X
ACLK1
to
X
X
X
Input
X
H*
X
X
NOTES:
to
BCLK1
X
X
X
Input
X
L
X
X
H = High voltage level
ACLK2
to
X
X
X
X
Input
X
H*
X
L
= Low voltage level
to
BCLK2
X
X
X
X
Input
X
L
X
h
= High voltage level one set-up time prior to
BCLK1
to
X
X
X
H
X
Input
X
X
Low to High ACLKin transition
to
ACLK1
X
X
X
L
X
Input
X
X
l
= Low voltage level one set-up time prior to
BCLK2
to
X
X
X
X
H
X
Input
X
Low to High ACLKin transition
to
ACLK2
X
X
X
X
L
X
Input
X
= Low to High transition
APAR
to
X
X
Input
X
X
X
H*
X
Z = High impedance (off) state
to
BCLK2
X
X
Input
X
X
X
L
X
H* = Goes to level of pull-up voltage
BCLK2
to
X
X
X
X
X
X
Input
H*
X = Don't care
to
AFPIn
X
X
X
X
X
X
Input
L
O = Output
BCLK1
to
X
X
H
X
X
Input
X
X
to
ACLKin
X
X
L
X
X
Input
X
X
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