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Электронный компонент: 74ALS109AN

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Philips
Semiconductors
74ALS109A
Dual J-K positive edge-triggered flip-flop
with set and reset
Product specification
1991 Feb 08
INTEGRATED CIRCUITS
IC05 Data Handbook
Philips Semiconductors
Product specification
74ALS109A
Dual J-K positive edge triggered flip-flop
with set and reset
2
1991 Feb 08
8531275 01670
DESCRIPTION
The 74ALS109A is a dual positive edge-triggered JK-type flip-flop
featuring individual J, K, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active-Low inputs and operate independently of the clock (CP) input.
The J and K are edge-triggered inputs which control the state
changes of the flip-flops as described in the function table. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. The J and K inputs must
be stable just one setup time prior to the Low-to-High transition of
the clock for predictable operation. The JK design allows operation
as a D flip-flop by tying J and K inputs together. Although the clock
input is level sensitive, the positive transition of the clock pulse
between the 0.8V and 2.0V levels should be equal to or less than
the clock to output delay time for reliable operation.
TYPE
TYPICAL
f
MAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74ALS109A
150MHz
3.0mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
10%,
T
amb
= 0
C to +70
C
DRAWING
NUMBER
16-pin plastic DIP
74ALS109AN
SOT38-4
16-pin plastic SO
74ALS109AD
SOT109-1
PIN CONFIGURATION
16
15
14
13
12
11
10
7
6
5
4
3
2
1
Q0
V
CC
CP1
SD1
Q1
K1
RD1
J1
RD0
J0
Q0
K0
CP0
SD0
9
8
GND
Q1
SF00135
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
J0, J1
J inputs
1.0/2.0
20
A/0.2mA
K0, K1
K inputs
1.0/2.0
20
A/0.2mA
CP0, CP1
Clock inputs (active rising edge)
1.0/2.0
20
A/0.2mA
SD0, SD1
Set inputs (active-Low)
1.0/4.0
20
A/0.4mA
RD0, RD1
Reset inputs (active-Low)
1.0/4.0
20
A/0.4mA
Q0, Q1, Q0, Q1
Data outputs
20/80
0.4mA/8mA
NOTE:
One (1.0) ALS unit load is defined as: 20
A in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
J1
J0
Q0 Q0 Q1 Q1
V
CC
= Pin 16
GND = Pin 8
K1
K0
2 14 3 13
6 7 10 9
CP0
SD0
RD0
CP1
SD1
RD1
4
5
1
12
11
15
SF00136
IEC/IEEE SYMBOL
SF00137
7
2
4
3
1
5
14
12
13
15
11
6
10
9
1J
C1
1K
R
S
2J
C2
2K
R
S
Philips Semiconductors
Product specification
74ALS109A
Dual J-K positive edge triggered flip-flop
with set and reset
1991 Feb 08
3
LOGIC DIAGRAM
VCC
=
Pin 16
GND = Pin 8
4, 12
SC00042
SD
RD
5, 11
1, 15
CP
J
K
2, 14
3, 13
6, 10
7, 9
Q
Q
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
SD
RD
CP
J
K
Q
Q
MODE
L
H
X
X
X
H
L
Asynchronous set
H
L
X
X
X
L
H
Asynchronous reset
L
L
X
X
X
H*
H*
Undetermined*
H
H
h
l
q
q
Toggle
H
H
l
l
L
H
Load "0"
H
H
h
h
H
L
Load "1"
H
H
l
h
q
q
Hold "no change"
H
H
L
l
h
q
q
Hold "no change"
H = High voltage level
h
= High state must be present one setup time prior to
Low-to-High clock transition
L
= Low voltage level
l
= Low state must be present one setup time prior to
Low-to-High clock transition
q
= Lower case indicate the state of the referenced output prior to
the Low-to-High clock transition
X = Don't care
= Low-to-High clock transition
*
= The output levels in this configuration are not guaranteed to
meet the minimum levels for V
OH
if the set and reset are near
V
IN
maximum. Furthermore, this configuration is nonstable;
that is, it will not remain when either set or reset returns to its
inactive (High) level.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
0.5 to +7.0
V
V
IN
Input voltage
0.5 to +7.0
V
I
IN
Input current
30 to +5
mA
V
OUT
Voltage applied to output in high output state
0.5 to V
CC
V
I
OUT
Current applied to output in Low output state
16
mA
T
amb
Operating free-air temperature range
0 to +70
C
T
stg
Storage temperature range
65 to +150
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
NOM
MAX
UNIT
V
CC
Supply voltage
4.5
5.0
5.5
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
I
Ik
Input clamp current
18
mA
I
OH
High-level output current
0.4
mA
I
OL
Low-level output current
8
mA
T
amb
Operating free-air temperature range
0
+70
C
Philips Semiconductors
Product specification
74ALS109A
Dual J-K positive edge triggered flip-flop
with set and reset
1991 Feb 08
4
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
1
MIN
TYP
2
MAX
UNIT
V
OH
High-level output voltage
V
CC
=
10%,
V
IL
= MAX, V
IH
= MIN
I
OH
= 0.4mA
V
CC
2
V
V
O
Low level output voltage
V
CC
= MIN, V
IL
= MAX,
I
OL
= 4mA
0.25
0.40
V
V
OL
Low-level output voltage
CC
,
IL
,
V
IH
= MIN
I
OL
= 8mA
0.35
0.50
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
0.73
1.5
V
I
Input current at maximum input
Jn, Kn, CPn
V
CC
= MAX V = 7 0V
0.1
mA
I
I
voltage
SDn, RDn
V
CC
= MAX, V
I
= 7.0V
0.2
mA
I
High level input current
Jn, Kn, CPn
V
CC
= MAX V = 2 7V
20
A
I
IH
Highlevel input current
SDn, RDn
V
CC
= MAX, V
I
= 2.7V
40
A
I
Low level input current
Jn, Kn, CPn
V
CC
= MAX V = 0 4V
0.2
mA
I
IL
Lowlevel input current
SDn, RDn
V
CC
= MAX, V
I
= 0.4V
0.4
mA
I
O
Output current
3
V
CC
= MAX, V
O
= 2.25V
30
112
mA
I
CC
Supply current (total)
4
V
CC
= MAX
3.0
4.0
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
C.
3. The output conditions have been chosen to produce a current that closely approximates one half of the true shortcircuit output current, I
OS
.
4. Measure I
CC
with the clock input grounded and all outputs open, then with Q and Q outputs High in turn.
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
T
amb
= 0
C to +70
C
V
CC
= +5.0V
10%
C
L
= 50pF, R
L
= 500
UNIT
MIN
MAX
f
MAX
Maximum clock frequency
Waveform 1
80
MHz
t
PLH
t
PHL
Propagation delay
CPn to Qn or Qn
Waveform 1
3.0
3.0
14.0
14.0
ns
t
PLH
t
PHL
Propagation delay
SDn or RD to Qn or Qn
Waveform 2, 3
1.0
3.0
8.0
10.0
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
T
amb
= 0
C to +70
C
V
CC
= +5.0V
10%
C
L
= 50pF, R
L
= 500
UNIT
MIN
MAX
t
su
(H)
t
su
(L)
Setup time, High or Low
Jn, Kn to CPn
Waveform 1
6.0
6.0
ns
t
h
(H
)
t
h (
L
)
Hold time, High or Low
Jn, Kn to CPn
Waveform 1
0.0
0.0
ns
t
w
(H)
t
w
(L)
CPn Pulse width
High or Low
Waveform 1
6.0
6.0
ns
t
w
(L)
SDn or RDn Pulse width
Low
Waveform 2, 3
6.0
ns
t
rec
Recovery time, SDn or RDn to CPn
Waveform 2, 3
6.0
ns
Philips Semiconductors
Product specification
74ALS109A
Dual J-K positive edge triggered flip-flop
with set and reset
1991 Feb 08
5
AC WAVEFORMS
For all waveforms, V
M
= 1.3V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VM
VM
CPn
VM
VM
VM
VM
VM
VM
tsu(H)
th(H)
Jn,
Kn
Qn
VM
tw(H)
1/fmax
tsu(L)
th(L)
VM
VM
tPLH
Qn
tw(L)
tPHL
tPHL
tPLH
SC00043
Waveform 1.
Propagation Delay for Data to Output,
Data Setup Time and Hold Times, Clock Width,
and Maximum Clock Frequency
VM
CPn
Qn
VM
VM
Qn
tPHL
tPLH
SDn
VM
VM
tw(L)
SC00044
Jn, Kn
tREC
Waveform 2.
Propagation Delay for Set to Output,
Set Pulse Width and Recovery Time for Set to Clock
VM
CPn
Qn
VM
VM
Qn
tPHL
tPLH
RDn
VM
VM
tw(L)
SC00045
Jn, Kn
tREC
Waveform 3.
Propagation Delay for Reset to Output,
Reset Pulse Width and Recovery Time for Reset to Clock
Philips Semiconductors
Product specification
74ALS109A
Dual J-K positive edge triggered flip-flop
with set and reset
1991 Feb 08
6
TEST CIRCUIT AND WAVEFORMS
tw
90%
VM
10%
90%
VM
10%
90%
VM
10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
tw
AMP (V)
0.3V
0.3V
tTHL (tf
f
)
INPUT PULSE REQUIREMENTS
Rep.Rate
t
w
t
TLH
t
THL
1MHz
500ns
2.0ns
2.0ns
Input Pulse Definition
VCC
Family
74ALS
D.U.T.
PULSE
GENERATOR
RL
CL
RT
VIN
VOUT
Test Circuit for Totem-pole Outputs
DEFINITIONS:
R
L
= Load resistor;
see AC electrical characteristics for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
tTHL (tf
)
tTLH (tr
)
tTLH (tr
)
AMP (V)
Amplitude
3.5V
1.3V
V
M
SC00005
Dual J-K positive edge-triggered flip-flop
with set and reset
Philips Semiconductors
Product specification
74ALS109A
1991 Feb 08
7
DIP16:
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
Dual J-K positive edge-triggered flip-flop
with set and reset
Philips Semiconductors
Product specification
74ALS109A
1991 Feb 08
8
SO16:
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
Dual J-K positive edge-triggered flip-flop
with set and reset
Philips Semiconductors
Product specification
74ALS109A
1991 Feb 08
9
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381
DEFINITIONS
Data Sheet Identification
Product Status
Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
Philips
Semiconductors