2003 May 14
2
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
FEATURES
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
MultiByte flow-through standard pin-out architecture
Low inductance multiple V
CC
and GND pins for minimum
noise and ground bounce
Direct interface with TTL levels
Bus hold on data inputs (74ALVCH16244 only)
Output drive capability 50
transmission lines at 85
C
Current drive
24 mA at 3.0 V
Complies with JEDEC standard no. 8-1 A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74ALVC16244; 74ALVCH16244 is a 16-bit
non-inverting buffer/line driver with 3-state outputs. The
device can be used as four 4-bit buffers, two 8-bit buffers
or one 16-bit buffer. The 3-state outputs are controlled by
the output enable inputs 1OE, 2OE, 3OE and 4OE. A
HIGH on nOE causes the outputs to assume a
high-impedance OFF-state.
The 74ALVCH16244 has active bus hold circuitry which is
provided to hold unused or floating data inputs at a valid
logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
The 74ALVC16244 has 5 V tolerant inputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
2.5 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
N +
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
SYMBOL
PARAMETERS
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay nAn to nYn
V
CC
= 2.5 V; C
L
= 30 pF
1.9
ns
V
CC
= 3.3 V; C
L
= 50 pF
1.9
ns
C
I
input capacitance
5.0
pF
C
PD
power dissipation capacitance per buffer
notes 1 and 2
outputs enabled
25
pF
outputs disabled
4
pF
2003 May 14
4
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
PINNING
PIN
SYMBOL
DESCRIPTION
1
1OE
output enable input (active LOW)
2
1Y0
data output
3
1Y1
data output
4
GND
ground (0 V)
5
1Y2
data output
6
1Y3
data output
7
V
CC
supply voltage
8
2Y0
data output
9
2Y1
data output
10
GND
ground (0 V)
11
2Y2
data output
12
2Y3
data output
13
3Y0
data output
14
3Y1
data output
15
GND
ground (0 V)
16
3Y2
data output
17
3Y3
data output
18
V
CC
supply voltage
19
4Y0
data output
20
4Y1
data output
21
GND
ground (0 V)
22
4Y2
data output
23
4Y3
data output
24
4OE
output enable input (active LOW)
25
3OE
output enable input (active LOW)
26
4A3
data input
27
4A2
data input
28
GND
ground (0 V)
29
4A1
data input
30
4A0
data input
31
V
CC
supply voltage
32
3A3
data input
33
3A2
data input
34
GND
ground (0 V)
35
3A1
data input
36
3A0
data input
37
2A3
data input
38
2A2
data input
39
GND
ground (0 V)
40
2A1
data input
41
2A0
data input
42
V
CC
supply voltage
43
1A3
data input
44
1A2
data input
45
GND
ground (0 V)
46
1A1
data input
47
1A0
data input
48
2OE
output enable input (active LOW)
PIN
SYMBOL
DESCRIPTION
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