Document Outline
- FEATURES
- DESCRIPTION
- QUICK REFERENCE DATA
- ORDERING INFORMATION
- FUNCTION TABLE
- PINNING
- RECOMMENDED OPERATING CONDITIONS
- LIMITING VALUES
- DC CHARACTERISTICS
- AC CHARACTERISTICS
- AC WAVEFORMS
- PACKAGE OUTLINES
- SOLDERING
- DATA SHEET STATUS
- DEFINITIONS
- DISCLAIMERS
DATA SHEET
Product specification
File under Integrated Circuits, IC24
2002 Feb 26
INTEGRATED CIRCUITS
74ALVC373
Octal D-type transparent latch;
3-state
2002 Feb 26
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
FEATURES
Wide supply voltage range from 1.65 to 3.6 V
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
3.6 V tolerant inputs/outputs
CMOS LOW power consumption
Direct interface with TTL levels (2.7 to 3.6 V)
Power-down mode
Latch-up performance exceeds
250 mA
ESD protection:
2000 V Human Body Model (JESD22-A114-A)
200 V Machine Model (JESD22-A115-A).
DESCRIPTION
The 74ALVC373 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
The 74ALVC373 is an octal D-type transparent latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all
internal latches.
The 74ALVC373 consists of eight D-type transparent
latches with 3-state true outputs. When LE is HIGH, data
at the D
n
inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state
each time its corresponding D-input changes.
When LE is LOW the latches store the information that
was present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the 8 latches are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The `373' is functionally identical to the `573', but the `573'
have a different pin arrangement.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
+ (C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
and the latch is in transparent mode.
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
t
PHL
/t
PLH
propagation delay inputs D
n
to output Q
n
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 k
3.0
ns
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
2.3
ns
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
2.4
ns
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
2.2
ns
C
I
input capacitance
3.5
pF
C
PD
power dissipation capacitance per buffer
V
CC
= 3.3 V; notes 1 and 2
outputs enable
35
pF
outputs disabled
14
pF
2002 Feb 26
3
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
ORDERING INFORMATION
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don't care;
Z = high-impedance OFF-state.
PINNING
TYPE NUMBER
PACKAGES
PINS
PACKAGE
MATERIAL
CODE
74ALVC373D
20
SO
plastic
SOT163-1
74ALVC373PW
20
TSSOP
plastic
SOT360-1
OPERATING MODES
INPUT
INTERNAL
LATCHES
OUTPUTS
OE
LE
D
n
Q
0
to Q
7
Enable and read register
(transparent mode)
L
H
L
L
L
L
H
H
H
H
Latch and read register
L
L
l
L
L
L
L
h
H
H
Latch register and disable
outputs
H
X
X
X
Z
H
L
h
H
Z
PIN
SYMBOL
DESCRIPTION
1
OE
output enable input (active LOW)
2, 5, 6, 9, 12, 15, 16, 19
Q
0
to Q
7
3-state latch output
3, 4, 7, 8, 13, 14, 17, 18
D
0
to D
7
data input
10
GND
ground (0 V)
11
LE
latch enable input (active HIGH)
20
V
CC
supply voltage
2002 Feb 26
4
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
Fig.1 Pin configuration.
handbook, halfpage
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
VCC
Q7
D7
D6
Q5
D5
Q6
D4
Q4
LE
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
373
MNA185
handbook, halfpage
MNA186
D0
D1
D2
D3
D4
D5
D6
D7
OE
LE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
11
1
19
16
15
12
9
6
5
2
18
17
14
13
8
7
4
3
Fig.2 Logic symbol.
handbook, halfpage
MNA187
19
16
15
12
9
6
5
11
C1
1
EN
1D
2
18
17
14
13
8
7
4
3
Fig.3 IEE/IEC logic symbol.
handbook, halfpage
MNA184
3-STATE
OUTPUTS
LATCH
1 to 8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7 19
16
15
12
9
6
5
2
D0
D1
D2
D3
D4
D5
D6
D7
LE
OE
18
11
1
17
14
13
8
7
4
3
Fig.4 Function diagram.
2002 Feb 26
5
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
handbook, halfpage
Q
LE
D
LE
LE
LE
MNA692
Fig.5 Logic diagram (one latch).
handbook, full pagewidth
MNA199
Q4
D4
D
LE
Q
Q3
D3
D
LE
Q
Q2
D2
D
LE
Q
Q1
D1
D
LE
LE
LE
Q
Q0
D0
D
LATCH
1
LATCH
2
LATCH
3
LATCH
4
LATCH
5
Q
LE
OE
LE
LE
LE
LE
Q5
D5
D
LE
Q
LATCH
6
LE
Q6
D6
D
LE
Q
LATCH
7
LE
Q7
D7
D
LE
Q
LATCH
8
LE
Fig.6 Logic diagram.
2002 Feb 26
6
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When V
CC
= 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CC
supply voltage
1.65
3.6
V
V
I
input voltage
0
3.6
V
V
O
output voltage
enable mode; V
CC
= 1.65 to 3.6 V 0
V
CC
V
disable mode; V
CC
= 1.65 to 3.6 V 0
3.6
V
Power-down mode; V
CC
= 0 V
0
3.6
V
T
amb
operating ambient temperature
-
40
+85
C
t
r
, t
f
input rise and fall times
V
CC
= 1.65 to 2.7 V
0
20
ns/V
V
CC
= 2.7 to 3.6 V
0
10
ns/V
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CC
supply voltage
-
0.5
+4.6
V
I
IK
input diode current
V
I
< 0
-
-
50
mA
V
I
input voltage
-
0.5
+4.6
V
I
OK
output diode current
V
O
> V
CC
or V
O
< 0
-
50
mA
V
O
output voltage
enable mode; notes 1 and 2
-
0.5
V
CC
+ 0.5
V
disable mode
-
0.5
+4.6
V
Power-down mode; note 2
-
0.5
+4.6
V
I
O
output diode current
V
O
= 0 to V
CC
-
50
mA
I
GND
, I
CC
V
CC
or GND current
-
100
mA
T
stg
storage temperature
-
65
+150
C
P
tot
power dissipation per package
SO package
above 70
C derate linearly with
8 mW/K
-
500
mW
TSSOP package
above 60
C derate linearly with
5.5 mW/K
-
500
mW
2002 Feb 26
7
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Notes
1. All typical values are measured at V
CC
= 3.3 V and T
amb
= 25
C.
2. For transceivers, the parameter I
OZ
includes the input leakage current.
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
(
C)
UNIT
OTHER
V
CC
(V)
-
40 to +85
MIN.
TYP.
(1)
MAX.
V
IH
HIGH-level input
voltage
1.65 to 1.95
0.65
V
CC
-
-
V
2.3 to 2.7
1.7
-
-
V
2.7 to 3.6
2
-
-
V
V
IL
LOW-level input
voltage
1.65 to 1.95
-
-
0.35
V
CC
V
2.3 to 2.7
-
-
0.7
V
2.7 to 3.6
-
-
0.8
V
V
OL
LOW-level output
voltage
V
I
= V
IH
or V
IL
; I
O
= 100
A
1.65 to 3.6
-
-
0.2
V
V
I
= V
IH
or V
IL
; I
O
= 6 mA
1.65
-
0.11
0.3
V
V
I
= V
IH
or V
IL
; I
O
= 12 mA
2.3
-
0.17
0.4
V
V
I
= V
IH
or V
IL
; I
O
= 18 mA
2.3
-
0.25
0.6
V
V
I
= V
IH
or V
IL
; I
O
= 12 mA
2.7
-
0.16
0.4
V
V
I
= V
IH
or V
IL
; I
O
= 18 mA
3.0
-
0.23
0.4
V
V
I
= V
IH
or V
IL
; I
O
= 24 mA
3.0
-
0.30
0.55
V
V
OH
HIGH-level output
voltage
V
I
= V
IH
or V
IL
; I
O
=
-
100
A 1.65 to 3.6
V
CC
-
0.2
-
-
V
V
I
= V
IH
or V
IL
; I
O
=
-
6 mA
1.65
1.25
1.51
-
V
V
I
= V
IH
or V
IL
; I
O
=
-
12 mA
2.3
1.8
2.10
-
V
V
I
= V
IH
or V
IL
; I
O
=
-
18 mA
2.3
1.7
2.01
-
V
V
I
= V
IH
or V
IL
; I
O
=
-
12 mA
2.7
2.2
2.53
-
V
V
I
= V
IH
or V
IL
; I
O
=
-
18 mA
3.0
2.4
2.76
-
V
V
I
= V
IH
or V
IL
; I
O
=
-
24 mA
3.0
2.2
2.68
-
V
I
I
input leakage
current
V
I
= 3.6 V or GND
3.6
-
0.1
5
A
I
OZ
3-state output
OFF-state current
V
I
= V
IH
or V
IL
;
V
O
= 3.6 V or GND; note 2
1.65 to 3.6
-
0.1
10
A
I
off
power OFF leakage
current
V
I
or V
O
= 0 to 3.6 V
0.0
-
0.1
10
A
I
CC
quiescent supply
current
V
I
= V
CC
or GND; I
O
= 0
3.6
-
0.2
10
A
I
CC
additional
quiescent supply
current per input
pin
V
I
= V
CC
-
0.6 V; I
O
= 0
3.0 to 3.6
-
5
750
A
2002 Feb 26
8
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
AC CHARACTERISTICS
Note
1. All typical values are measured at T
amb
= 25
C.
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
(
C)
UNIT
WAVEFORMS
V
CC
(V)
-
40 to +85
MIN.
TYP.
(1)
MAX.
t
PHL
/t
PLH
propagation delay D
n
to Q
n
see Figs 7 and 11
1.65 to 1.95
1.0
2.5
5.4
ns
2.3 to 2.7
1.0
2.0
3.5
ns
2.7
1.0
2.3
3.6
ns
3.0 to 3.6
1.0
2.2
3.3
ns
t
PHL
/t
PLH
propagation delay LE to Q
n
see Figs 8 and 11
1.65 to 1.95
1.0
2.8
6.0
ns
2.3 to 2.7
1.0
2.1
3.8
ns
2.7
1.0
2.4
3.7
ns
3.0 to 3.6
1.0
2.3
3.3
ns
t
PZH
/t
PZL
3-state output enable time
OE to Q
n
see Figs 9 and 11
1.65 to 1.95
1.5
3.0
6.4
ns
2.3 to 2.7
1.0
2.4
4.5
ns
2.7
1.5
3.0
4.6
ns
3.0 to 3.6
1.0
2.3
4.0
ns
t
PHZ
/t
PLZ
3-state output disable time
OE to Q
n
see Figs 9 and 11
1.65 to 1.95
1.5
3.4
7.0
ns
2.3 to 2.7
1.0
2.2
4.4
ns
2.7
1.5
2.8
4.4
ns
3.0 to 3.6
1.0
2.7
4.4
ns
t
W
LE pulse with HIGH
see Figs 8 and 11
1.65 to 1.95
3.8
1.0
-
ns
2.3 to 2.7
3.3
0.8
-
ns
2.7
3.3
2.0
-
ns
3.0 to 3.6
3.3
2.2
-
ns
t
su
set-up time D
n
to LE
see Figs 10 and 11
1.65 to 1.95
0.8
0.1
-
ns
2.3 to 2.7
0.8
0.1
-
ns
2.7
0.8
0.1
-
ns
3.0 to 3.6
0.8
0.1
-
ns
t
h
hold time D
n
to LE
see Figs 10 and 11
1.65 to 1.95
0.8
-
0.1
-
ns
2.3 to 2.7
0.8
-
0.2
-
ns
2.7
0.8
-
0.3
-
ns
3.0 to 3.6
0.7
-
0.1
-
ns
2002 Feb 26
9
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
AC WAVEFORMS
handbook, halfpage
MNA693
Dn input
Qn output
tPHL
tPLH
GND
VI
VM
VM
VOH
VOL
Fig.7 Input D
n
to output Q
n
propagation delay times.
V
CC
V
M
INPUT
V
I
t
r
= t
f
1.65 to 1.95 V
0.5
V
CC
V
CC
2.0 ns
2.3 to 2.7 V
0.5
V
CC
V
CC
2.0 ns
2.7 V
1.5 V
2.7 V
2.5 ns
3.0 to 3.6 V
1.5 V
2.7 V
2.5 ns
handbook, full pagewidth
MNA694
LE input
Qn output
tPHL
tPLH
tW
1/fmax
VM
VOH
VI
GND
VOL
VM
Fig.8 Latch enable (LE) input pulse width and latch enable input to output (Q
n
) propagation delays.
V
CC
V
M
INPUT
V
I
t
r
= t
f
1.65 to 1.95 V
0.5
V
CC
V
CC
2.0 ns
2.3 to 2.7 V
0.5
V
CC
V
CC
2.0 ns
2.7 V
1.5 V
2.7 V
2.5 ns
3.0 to 3.6 V
1.5 V
2.7 V
2.5 ns
2002 Feb 26
10
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
handbook, full pagewidth
MNA395
tPLZ
tPHZ
outputs
disabled
outputs
enabled
VY
VX
outputs
enabled
Qn output
LOW-to-OFF
OFF-to-LOW
Qn output
HIGH-to-OFF
OFF-to-HIGH
OE input
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
Fig.9 3-state enable and disable times.
V
CC
V
M
INPUT
V
I
t
r
= t
f
1.65 to 1.95 V
0.5
V
CC
V
CC
2.0 ns
2.3 to 2.7 V
0.5
V
CC
V
CC
2.0 ns
2.7 V
1.5 V
2.7 V
2.5 ns
3.0 to 3.6 V
1.5 V
2.7 V
2.5 ns
V
OL
and V
OH
are typical output voltage drop that occur with the output load.
V
X
= V
OL
+ 0.3 V at V
CC
2.7 V;
V
X
= V
OL
+ 0.15 V at V
CC
< 2.7 V;
V
Y
= V
OH
-
0.3 V at V
CC
2.7 V;
V
Y
= V
OH
-
0.15 V at V
CC
< 2.7 V.
2002 Feb 26
11
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
handbook, full pagewidth
MNA695
th
tsu
th
tsu
VM
VM
VI
GND
VI
GND
LE input
Dn input
Fig.10 The data set-up and hold times for D
n
input to LE input.
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
CC
V
M
INPUT
V
I
t
r
= t
f
1.65 to 1.95 V
0.5
V
CC
V
CC
2.0 ns
2.3 to 2.7 V
0.5
V
CC
V
CC
2.0 ns
2.7 V
1.5 V
2.7 V
2.5 ns
3.0 to 3.6 V
1.5 V
2.7 V
2.5 ns
handbook, full pagewidth
VEXT
VCC
VI
VO
MNA616
D.U.T.
CL
RT
RL
RL
PULSE
GENERATOR
Fig.11 Load circuitry for switching times.
R
L
= Load resistor.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to the output impedance Z
o
of the pulse generator.
V
CC
V
I
C
L
R
L
V
EXT
t
PLH
/t
PHL
t
PZH
/t
PHZ
t
PZL
/t
PLZ
1.65 to 1.95 V
V
CC
30 pF
1 k
open
GND
2
V
CC
2.3 to 2.7 V
V
CC
30 pF
500
open
GND
2
V
CC
2.7 V
2.7 V
50 pF
500
open
GND
6 V
3.0 to 3.6 V
2.7 V
50 pF
500
open
GND
6 V
2002 Feb 26
12
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
PACKAGE OUTLINES
UNIT
A
max.
A
1
A
2
A
3
b
p
c
D
(1)
E
(1)
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
inches
2.65
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
1.27
10.65
10.00
1.1
1.0
0.9
0.4
8
0
o
o
0.25
0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
1.1
0.4
SOT163-1
10
20
w
M
b
p
detail X
Z
e
11
1
D
y
0.25
075E04
MS-013
pin 1 index
0.10
0.012
0.004
0.096
0.089
0.019
0.014
0.013
0.009
0.51
0.49
0.30
0.29
0.050
1.4
0.055
0.419
0.394
0.043
0.039
0.035
0.016
0.01
0.25
0.01
0.004
0.043
0.016
0.01
0
5
10 mm
scale
X
A
A
1
A
2
H
E
L
p
Q
E
c
L
v
M
A
(A )
3
A
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
97-05-22
99-12-27
2002 Feb 26
13
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
UNIT
A
1
A
2
A
3
b
p
c
D
(1)
E
(2)
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
0.65
6.6
6.2
0.4
0.3
0.5
0.2
8
0
o
o
0.13
0.1
0.2
1.0
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT360-1
MO-153
95-02-04
99-12-27
w
M
b
p
D
Z
e
0.25
1
10
20
11
pin 1 index
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v
M
A
X
A
y
0
2.5
5 mm
scale
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
A
max.
1.10
2002 Feb 26
14
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
"Data Handbook IC26; Integrated Circuit Packages"
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatures range from
215 to 250
C. The top-surface temperature of the
packages should preferable be kept below 220
C for
thick/large packages, and below 235
C for small/thin
packages.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
For packages with leads on two sides and a pitch (e):
larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
For packages with leads on four sides, the footprint must
be placed at a 45
angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250
C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300
C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320
C.
2002 Feb 26
15
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45
angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE
SOLDERING METHOD
WAVE
REFLOW
(1)
BGA, LFBGA, SQFP, TFBGA
not suitable
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not suitable
(2)
suitable
PLCC
(3)
, SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended
(3)(4)
suitable
SSOP, TSSOP, VSO
not recommended
(5)
suitable
2002 Feb 26
16
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
DATA SHEET STATUS
(1)
PRODUCT
STATUS
(2)
DEFINITIONS
Objective data
Development
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
DEFINITIONS
Short-form specification
The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition
Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications
These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
2002 Feb 26
17
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
NOTES
2002 Feb 26
18
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
NOTES
2002 Feb 26
19
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
NOTES
Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands
613508/01/pp
20
Date of release:
2002 Feb 26
Document order number:
9397 750 09437
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