2003 May 26
2
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74ALVC74
FEATURES
Wide supply voltage range from 1.65 to 3.6 V
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74ALVC74 is a dual positive-edge triggered, D-type
flip-flop with individual data (D), clock (CP), set (SD) and
reset (RD) inputs and complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
N +
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay nCP to nQ, nQ
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 k
3.7
ns
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
2.6
ns
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
2.8
ns
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
2.7
ns
t
PHL
/t
PLH
propagation delay nSD, nRD to nQ, nQ
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 k
3.5
ns
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
2.5
ns
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
3.1
ns
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
2.3
ns
f
max
maximum clock frequency
425
MHz
C
I
input capacitance
3.5
pF
C
PD
power dissipation capacitance per buffer
V
CC
= 3.3 V; notes 1 and 2
35
pF
2003 May 26
3
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74ALVC74
ORDERING INFORMATION
FUNCTION TABLES
Table 1
See note 1
Table 2
See note 1
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don't care;
= LOW-to-HIGH CP transition;
Q
n+1
= state after the next LOW-to-HIGH transition of CP.
TYPE NUMBER
PACKAGE
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
74ALVC74D
-
40 to +85
C
14
SO14
plastic
SOT108-1
74ALVC74PW
-
40 to +85
C
14
TSSOP14
plastic
SOT402-1
74ALVC74BQ
-
40 to +85
C
14
DHVQFN14
plastic
SOT762-1
INPUT
OUTPUT
nSD
nRD
nCP
nD
nQ
nQ
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
INPUT
OUTPUT
nSD
nRD
nCP
nD
nQ
n+1
nQ
n+1
H
H
L
L
H
H
H
H
H
L
2003 May 26
4
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74ALVC74
PINNING
PIN
SYMBOL
DESCRIPTION
1
1RD
asynchronous reset-direct input
(active LOW)
2
1D
data input
3
1CP
clock input (LOW-to-HIGH,
edge-triggered)
4
1SD
asynchronous set-direct input
(active LOW)
5
1Q
true flip-flop output
6
1Q
complement flip-flop output
7
GND
ground (0 V)
8
2Q
complement flip-flop output
9
2Q
true flip-flop output
10
2SD
asynchronous set-direct input
(active LOW)
11
2CP
clock input (LOW-to-HIGH,
edge-triggered)
12
2D
data input
13
2RD
asynchronous reset-direct input
(active LOW)
14
V
CC
supply voltage
Fig.1 Pin configuration SO14 and TSSOP14.
handbook, halfpage
MNA417
74
1
2
3
4
5
6
7
8
14
13
12
11
10
9
1RD
1D
1CP
1SD
1Q
1Q
GND
2Q
2Q
2SD
2CP
2D
2RD
VCC
Fig.2 Pin configuration DHVQFN14.
handbook, halfpage
1
14
1RD
VCC
7
2
3
4
5
6
1D
1CP
1SD
1Q
1Q
13
12
11
10
9
2RD
2D
2CP
2SD
2Q
8
GND
2Q
GND
(1)
Top view
MDB105
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.3 Logic symbol.
MNA418
handbook, halfpage
RD
FF
SD
4 10
Q
1Q
2Q
1Q
2Q
5
9
2
12
3
11
6
8
Q
1SD
CP
2CP
1CP
2D
1D
D
2SD
1 13
1RD 2RD
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