Philips Semiconductors
Product specification
74ALVCH16843
18-bit bus interface D-type latch (3-State)
2
1998 Aug 04
8532108 019833
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive
24 mA at 3.0 V
MULTIBYTE
TM
flow-through standard pin-out architecture
Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
All data inputs have bus hold
Output drive capability 50
transmission lines @ 85
C
DESCRIPTION
The 74ALVCH16843 has two 9bit D-type latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. The two sections of each register are controlled
independently by the latch enable (nLE), clear (nCLR),
preset (nPRE) and output enable (nOE) control gates.
When nOE is LOW, the data in the registers appear at the outputs.
When nOE is HIGH, the outputs are in the high impedance OFF
state. Operation of the nOE input does not affect the state of the
flip-flops.
The 74ALVCH16843 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1OE
1Q
0
1Q
1
1Q
2
1Q
3
1Q
4
1Q
5
GND
V
CC
GND
1Q
6
1Q
7
1Q
8
2Q
0
2Q
1
2Q
2
GND
2Q
3
2Q
4
2Q
5
V
CC
2Q
6
2Q
7
GND
2Q
8
2CLR
1D
0
GND
1D
1
1D
2
V
CC
1D
3
1D
4
1D
5
GND
1D
6
1D
7
1D
8
2D
0
2D
1
2D
2
GND
2D
3
2D
4
2D
5
V
CC
2D
6
2D
7
GND
2D
8
2LE
1PRE
1CLR
2OE
1LE
2PRE
SH00143
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
C; t
r
= t
f
2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
nDn to nQn
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
2.2
2.1
ns
t
PHL
/t
PLH
Propagation delay
nLE to nQn
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
2.3
2.0
ns
C
I
Input capacitance
5.0
pF
C
PD
Power dissipation capacitance per buffer
V
I
= GND to V
CC
1
transparent mode
Output enabled
Output disabled
17
3
pF
C
PD
Power dissi ation ca acitance er buffer
V
I
= GND to V
CC
1
Clocked mode
Output enabled
Output disabled
19
9
F
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
S
(C
L
V
CC
2
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
V
CC
2
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
OUTSIDE NORTH
AMERICA
NORTH AMERICA
DRAWING
NUMBER
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
40
C to +85
C
74ALVCH16843 DGG
ACH16843 DGG
SOT364-1
Philips Semiconductors
Product specification
74ALVCH16843
18-bit bus interface D-type latch (3-State)
1998 Aug 04
3
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1
1CLR
Clear input (active LOW)
2
1OE
Output enable input (active
LOW)
55
1PRE
Preset input (active LOW)
56
1LE
Latch enable input (active
HIGH)
54, 52, 51, 49, 48,
47, 45, 44, 43
1D0 to 1D8
Data inputs
3, 5, 6, 8, 9,
10, 12, 13, 14
1Q0 to 1Q8
Data outputs
4, 11, 18, 25,
32, 39, 46, 53
GND
Ground (0V)
7, 22, 35, 50
V
CC
Positive supply voltage
27
2OE
Output enable input (active
LOW)
28
2CLR
Clear input (active LOW)
29
2LE
Latch enable input (active
HIGH)
30
2PRE
Preset input (active LOW)
42, 41, 40, 38, 37,
36, 34, 33, 31
2D0 to 2D8
Data inputs
15, 16, 17, 19, 20,
21, 23, 24, 26
2Q0 to 2Q8
Data outputs
FUNCTION TABLE
INPUTS
OUTPUT
nPRE
nCLR
nOE
LE
D
X
Q
L
X
L
X
X
H
H
L
L
X
X
L
H
H
L
H
L
L
H
H
L
H
H
H
H
H
L
H
X
Q
0
X
X
H
H
X
Z
H
=
HIGH voltage level
L
=
LOW voltage level
X
=
Don't care
Z
=
High impedance "off" state
LOGIC SYMBOL
54
52
51
49
48
47
45
44
41
40
38
37
36
34
33
31
3
5
6
8
9
10
12
13
16
17
19
20
21
23
24
26
1D
0
1D
1
1D
2
1D
3
1D
4
1D
5
1D
6
1D
7
1D
8
2D
0
2D
1
2D
2
2D
3
2D
4
2D
5
2D
6
2D
7
1Q
0
1Q
1
1Q
2
1Q
3
1Q
4
1Q
5
1Q
6
1Q
7
1Q
8
2Q
0
2Q
1
2Q
2
2Q
3
2Q
4
2Q
5
2Q
6
2Q
7
2D
8
2Q
8
1OE
1LE
2OE
2LE
2
56
27
29
SH00144
1CLR 1PRE
2CLR 2PRE
1
55
28
30
14
15
43
42
Philips Semiconductors
Product specification
74ALVCH16843
18-bit bus interface D-type latch (3-State)
1998 Aug 04
5
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
V
CC
DC supply voltage 2.5V range (for max. speed
performance @ 30 pF output load)
2.3
2.7
V
V
CC
DC supply voltage 3.3V range (for max. speed
performance @ 50 pF output load)
3.0
3.6
V
V
I
DC Input voltage range
0
V
CC
V
V
O
DC output voltage range
0
V
CC
V
T
amb
Operating free-air temperature range
40
+85
C
t
r
, t
f
Input rise and fall times
V
CC
= 2.3 to 3.0V
V
CC
= 3.0 to 3.6V
0
0
20
10
ns/V
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +4.6
V
I
IK
DC input diode current
V
I
t
0
50
mA
V
I
DC input voltage
For control pins
2
0.5 to +4.6
V
V
I
DC in ut voltage
For data inputs
2
0.5 to V
CC
+0.5
V
I
OK
DC output diode current
V
O
u
V
CC
or V
O
t
0
"
50
mA
V
O
DC output voltage
Note 2
0.5 to V
CC
+0.5
V
I
O
DC output source or sink current
V
O
= 0 to V
CC
"
50
mA
I
GND
, I
CC
DC V
CC
or GND current
"
100
mA
T
stg
Storage temperature range
65 to +150
C
P
TOT
Power dissipation per package
plastic medium-shrink (SSOP)
plastic thin-medium-shrink (TSSOP)
For temperature range: 40 to +125
C
above +55
C derate linearly with 11.3 mW/K
above +55
C derate linearly with 8 mW/K
850
600
mW
NOTE:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
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