Philips
Semiconductors
74ALVT16652
2.5V/3.3V 16-bit bus transceiver/register
(3-State)
Product specification
Supersedes data of 1996 Aug 13
IC23 Data Handbook
1998 Feb 13
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74ALVT16652
2.5V/3.3V 16-bit bus transceiver/register
(3-State)
2
1998 Feb 13
853-1854 18962
FEATURES
16bit bus interface
5V I/O Compatible
3-State buffers
Output capability: +64mA/-32mA
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-State
No bus current loading when output is tied to 5V bus
Latch-up protection exceeds 500mA per JEDEC JC40.2 Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ALVT16652 is a high-performance BiCMOS product
designed for V
CC
operation at 2.5V or 3.3V with I/O compatibility up
to 5V. The device can be used as two 8-bit transceivers or one
16-bit transceiver.
Complimentary output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions. Select-control (SAB
and SBA) inputs are provided to select whether real-time or stored
data is transferred. A Low-input level selects real-time data, and a
High input level selects stored data. The circuitry used for select
control eliminates the typical decoding glitch that occurs in a
multiplexer during the transition between stored and real-time data.
Data on the A or B bus, or both, can be stored in the internal
flip-flops by Low-to-High transitions at the appropriate clock (CPAB
or CPBA) inputs regardless of the levels on the select-control or
output-enable inputs. When SAB and SBA are in real-time transfer
mode, it is possible to store data without using the internal D-type
flip-flops by simultaneously enabling OEAB and OEBA. In this
configuration, each output reinforces its input. Thus, when all other
data sources to the two sets of bus lines are at high impedance,
each set of bus lines remains at its last level configuration.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
SYMBOL
PARAMETER
T
amb
= 25
C
2.5V
3.3V
UNIT
t
PLH
t
PHL
Propagation delay
nAx to nBx or nBx to nAx
C
L
= 50pF
2.0
2.1
1.5
1.6
ns
C
IN
Input capacitance DIR, OE
V
I
= 0V or V
CC
3
3
pF
C
I/O
I/O pin capacitance
V
I/O
= 0V or V
CC
9
9
pF
I
CCZ
Total supply current
Outputs disabled
40
70
A
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
40
C to +85
C
74ALVT16652 DL
AV16652 DL
SOT371-1
56-Pin Plastic TSSOP Type II
40
C to +85
C
74ALVT16652 DGG
AV16652 DGG
SOT364-1
LOGIC SYMBOL (IEEE/IEC)
56
1
55
54
2
5
6
8
9
10
12
13
14
3
EN1(BA)
EN2(AB)
C3
G4
C5
G6
w
1
1
5D
6
1
6
4
3D
4
1
w
1
2
52
51
49
48
47
45
44
43
29
28
30
31
27
26
15
16
17
19
20
21
23
24
42
41
40
38
37
36
34
33
w
1
7
11D 12
1 12
10
9D
10
1
w
1
8
EN7(BA)
EN8(AB)
C9
G10
C11
G12
SW00158
Philips Semiconductors
Product specification
74ALVT16652
2.5V/3.3V 16-bit bus transceiver/register
(3-State)
1998 Feb 13
3
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
27
28
30
29
1OEAB
1CPAB
1SAB
GND
1A0
1A1
1A2
1A3
1A4
GND
1A5
1A6
1A7
2A0
2A2
GND
2A3
VCC
2A1
2A4
2A5
2A6
2A7
2SAB
VCC
GND
2CPAB
20EAB
1OEBA
1CPBA
1SBA
GND
1B0
1B1
1B2
1B3
1B4
GND
1B5
1B6
1B7
2B0
2B2
GND
2B3
VCC
2B1
2B4
2B5
2B6
2B7
2SBA
VCC
GND
2CPBA
2OEBA
SH00046
LOGIC SYMBOL
2
3
1CPAB
1SAB
54
1SBA
55
1CPBA
1
1OEAB
56
1OEBA
27
26
2CPAB
2SAB
31
2SBA
30
2CPBA
28
2OEAB
29
2OEBA
5
6
8
9
10
12
13
14
52
51
49
48 47
45
44
43
15
16
17
19 20
21
23
24
42
41
40
38 37
36
34
33
1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7
1AB 1B1 1B2 1B3 1B4 1B5 1B6 1B7
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
2AB 2B1 2B2 2B3 2B4 2B5 2B6 2B7
SW00159
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
2, 55, 27, 30
1CPAB, 1CPBA, 2CPAB, 2CPBA
Clock input A to B / Clock input B to A
3, 54, 26, 31
1SAB, 1SBA, 2SAB, 2SBA
Select input A to B / Select input B to A
5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24
1A0 1A7,
2A0 2A7
Data inputs/outputs (A side)
52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33
1B0 1B7,
2B0 2B7
Data inputs/outputs (B side)
1, 56, 28, 29
1OEAB, 1OEBA,
2OEAB, 2OEBA
Output enable inputs
4, 11, 18, 25, 32, 39, 46, 53
GND
Ground (0V)
7, 22, 35, 50
V
CC
Positive supply voltage
Philips Semiconductors
Product specification
74ALVT16652
2.5V/3.3V 16-bit bus transceiver/register
(3-State)
1998 Feb 13
4
LOGIC DIAGRAM
1D
C1
Q
DETAIL A X 7
nB0
1D
C1
Q
nA0
1of 8 Channels
nA7
nA6
nA5
nA4
nA3
nA2
nA1
nB1
nB2
nB3
nB4
nB5
nB6
nB7
nOEBA
nOEAB
nCPBA
nSBA
nCPAB
nSAB
SH00065
FUNCTION TABLE
INPUTS
DATA I/O
OPERATING MODE
nOEAB
nOEBA
nCPAB
nCPBA
nSAB
nSBA
nAx
nBx
OPERATING MODE
L
L
H
H
H or L
H or L
X
X
X
X
Input
Input
Isolation
Store A and B data
X
H
H
H
H or L
X
**
X
X
Input
Unspecified
output*
Store A, Hold B
Store A in both registers
L
L
X
L
H or L
X
X
X
**
Unspecified
output*
Input
Hold A, Store B
Store B in both registers
L
L
L
L
X
X
X
H or L
X
X
L
H
Output
Input
Real time B data to A bus
Stored B data to A bus
H
H
H
H
X
H or L
X
X
L
H
X
X
Input
Output
Real time A data to B bus
Store A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus
Stored B data to A bus
H = High voltage level
L
= Low voltage level
X = Don't care
= Low-to-High clock transition
*
The data output function may be enabled or disabled by various signals at the nOEBA and nOEAB inputs. Data input functions are
always enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.
**
If both Select controls (nSAB and nSBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must
be staggered in order to load both registers.
Philips Semiconductors
Product specification
74ALVT16652
2.5V/3.3V 16-bit bus transceiver/register
(3-State)
1998 Feb 13
5
The following examples demonstrate the four fundamental
bus-management functions that can be performed with the
74ALVT16652. The select pins determine whether data is stored or
transferred through the device in real time. The output enable pins
determine the direction of the data flow.
}
REAL TIME BUS TRANSFER
BUS B TO BUS A
nOEAB nOEBA nCPAB nCPBA nSAB nSBA
L
L
X
X
X
L
}
REAL TIME BUS TRANSFER
BUS A TO BUS B
nOEAB nOEBA nCPAB nCPBA nSAB nSBA
H
H
X
X
L
X
}
STORAGE FROM
A, B, OR A AND B
nOEAB nOEBA nCPAB nCPBA nSAB nSBA
X
H
X
X
X
L
X
X
X
X
L
H
X
X
}
TRANSFER STORED DATA
TO A OR B
nOEAB nOEBA nCPAB nCPBA nSAB nSBA
H
L
H | L
H | L
H
H
A
B
A
B
A
B
A
B
SH00066
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