DATA SHEET
Product Specification
Supersedes data of 1998 Dec 11
File under Integrated Circuits, IC24
2000 Mar 09
INTEGRATED CIRCUITS
74AVC16374
16-bit edge triggered D-type
flip-flop; 3.6 V tolerant; 3-state
2000 Mar 09
2
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant;
3-state
74AVC16374
FEATURES
Wide supply voltage range from 1.2 to 3.6 V
Complies with JEDEC standard no. 8-1A/5/7
CMOS low power consumption
Input/output tolerant up to 3.6 V
DCO (Dynamic Controlled Output) circuit dynamically
changes output impedance, resulting in noise reduction
without speed degradation
Low inductance multiple V
CC
and GND pins to minimize
noise and ground bounce
Supports Live Insertion.
DESCRIPTION
The 74AVC16374 is a 16-bit edge triggered flip-flop
featuring separate D-type inputs for each flip-flop and
3-state outputs for bus oriented applications.
The 74AVC16374 consist of 2 sections of eight edge
triggered flip-flops. A clock input (CP) and an output
enable (OE) are provided per 8-bit section.
The 74AVC16374 is designed to have an extremely fast
propagation delay and a minimum amount of power
consumption.
To ensure the high-impedance output state during
power-up or power-down, nOE should be tied to V
CC
through a pull-up resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is
implemented to support termination line drive during
transient (see Figs 1 and 2).
Fig.1
Output voltage as a function of the
HIGH-level output current.
handbook, halfpage
0
1
2
4
0
-
200
-
300
-
100
MNA506
3
VOH (V)
IOH
(mA)
1.8 V
2.5 V
3.3 V
handbook, halfpage
0
1
2
4
300
100
0
200
MNA507
3
VOL (V)
IOL
(mA)
1.8 V
2.5 V
3.3 V
Fig.2
Output voltage as a function of the
LOW-level output current.
2000 Mar 09
3
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant;
3-state
74AVC16374
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
2.0 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
(C
L
V
CC
2
f
o
) = sum of outputs.
2. The condition is V
I
= GND to V
CC
.
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
Z = high impedance OFF-state;
= LOW-to-HIGH CP transition.
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
t
PHL
/t
PLH
propagation delay
nCP to nQ
n
V
CC
= 1.2 V
3.1
ns
V
CC
= 1.5 V
2.4
ns
V
CC
= 1.8 V
2.0
ns
V
CC
= 2.5 V
1.5
ns
V
CC
= 3.3 V
1.3
ns
f
max
maximum clock pulse
frequency
V
CC
= 1.2 V
250
MHz
V
CC
= 1.5 V
300
MHz
V
CC
= 1.8 V
320
MHz
V
CC
= 2.5 V
350
MHz
V
CC
= 3.3 V
350
MHz
C
I
input capacitance
5.0
pF
C
PD
power dissipation
capacitance per buffer
notes 1 and 2
outputs enabled
66
pF
outputs disabled
1
pF
OPERATING MODES
INPUTS
INTERNAL
FLIP-FLOPS
OUTPUTS
nOE
nCP
nD
n
nQ
n
Load and read register
L
L
l
h
L
H
L
H
Load register and disable outputs
H
H
l
h
L
H
Z
Z
2000 Mar 09
4
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant;
3-state
74AVC16374
ORDERING AND PACKAGE INFORMATION
PINNING
TYPE NUMBER
PACKAGE
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
74AVC16374DGG
-
40 to +85
C
48
TSSOP
plastic
SOT362-1
PIN
SYMBOL
DESCRIPTION
1
1OE
output enable input (active LOW)
2, 3, 5, 6, 8, 9, 11 and 12
1Q
0
to 1Q
7
3-state flip-flop outputs
4, 10, 15, 21, 28, 34, 39 and 45
GND
ground (0 V)
7, 18, 31 and 42
V
CC
DC supply voltage
13, 14, 16, 17, 19, 20, 22 and 23
2Q
0
to 2Q
7
3-state flip-flop outputs
24
2OE
output enable input (active LOW)
25
2CP
clock input
26, 27, 29, 30, 32, 33, 35 and 36
2D
7
to 2D
0
data inputs
37, 38, 40, 41, 43, 44, 46 and 47
1D
7
to 1D
0
data inputs
48
1CP
clock input
2000 Mar 09
5
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant;
3-state
74AVC16374
handbook, halfpage
16374
MNA575
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
25
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
1Q0
1Q1
GND
1Q2
1Q3
VCC
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
VCC
2Q4
2Q5
GND
2Q6
2Q7
2OE
1D0
1D1
GND
1D2
1D3
VCC
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
VCC
2D4
2D5
GND
2D6
2D7
2CP
1OE
1CP
Fig.3 Pin configuration.
handbook, halfpage
MNA576
1Q0
1Q1
1CP
2CP
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1OE
47
46
48
25
44
43
41
40
38
37
2
3
1
5
6
8
9
11
12
24
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
36
35
33
32
30
29
27
26
13
14
16
17
19
20
22
23
2OE
Fig.4 Logic symbol.
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