Philips Semiconductors
Product specification
74F193
Up/down binary counter with separate up/down clocks
2
1995 Jul 17
853-0353 15459
FEATURES
Synchronous reversible 4-bit counting
Asynchronous parallel load capability
Asynchronous reset (clear)
Cascadable without external logic
DESCRIPTION
The 74F193 is a 4-bit synchronous up/down counter in the binary
mode. Separate up/down clocks, CP
U
and CP
D
respectively,
simplify operation. The outputs change state synchronously with the
Low-to-High transition of either clock input. If the CP
U
clock is
pulsed while CP
D
is held High, the device will count up. If CP
D
clock
is pulsed while CP
U
is held High, the device will count down. The
device can be cleared at any time by the asynchronous reset pin. It
may also be loaded in parallel by activating the asynchronous
parallel load pin.
Inside the device are four master-slave JK flip-flops with the
necessary steering logic to provide the asynchronous reset,
asynchronous preset, load, and synchronous count up and count
down functions.
Each flip-flop contains JK feedback from slave to master, such that a
Low-to-High transition on the CP
D
input will decrease the count by
one, while a similar transition on the CP
U
input will advance the
count by one.
One clock should be held High while counting with the other,
because the circuit will either count by twos or not at all, depending
on the state of the first JK flip-flop, which cannot toggle as long as
either clock input is Low. Applications requiring reversible operation
must make the reversing decision while the activating clock is High
to avoid erroneous counts.
The Terminal Count Up (TC
U
) and Terminal Count Down (TC
D
)
outputs are normally High. When the circuit has reached the
maximum count state of 15, the next High-to-Low transition of CP
U
will cause TC
U
to go Low. TC
U
will stay Low until CP
U
goes High
again, duplicating the count up clock, although delayed by two gate
delays. Likewise, the TC
D
output will go Low when the circuit is in
the zero state and the CP
D
goes Low. The TC outputs can be used
as the clock input signals to the next higher order circuit in a
multistage counter, since they duplicate the clock waveforms.
Multistage counters will not be fully synchronous since there is a
two-gate delay time difference added for each stage that is added.
The counter may be preset by the asynchronous parallel load
capability of the circuit. Information present on the parallel Data
inputs (D0 - D3) is loaded into the counter and appears on the
outputs regardless of the conditions of the clock inputs when the
Parallel Load (PL) input is Low. A High level on the Master Reset
(MR) input will disable the parallel load gates, override both clock
inputs, and set all Q outputs Low. If one of the clock inputs is Low
during and after a reset or load operation, the next Low-to-High
transition of the clock will be interpreted as a legitimate signal and
will be counted.
TYPE
TYPICAL f
MAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F193
125MHz
32mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
10%,
T
amb
= 0
C to +70
C
PKG DWG #
16-pin plastic DIP
N74F193N
SOT38-4
16-pin plastic SO
N74F193D
SOT109-1
PIN CONFIGURATION
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
D1
Q1
Q0
CPD
CPU
Q2
Q3
D0
TCD
TCU
D2
D3
PL
GND
MR
VCC
SF00745
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 - D3
Data inputs
1.0/1.0
20
A/0.6mA
CP
U
Count up clock input (active rising edge)
1.0/3.0
20
A/1.8mA
CP
D
Count down clock input (active rising edge)
1.0/3.0
20
A/1.8mA
PL
Asynchronous parallel load control input (active Low)
1.0/1.0
20
A/0.6mA
MR
Asynchronous master reset input
1.0/1.0
20
A/0.6mA
Q0 - Q3
Flip-flop outputs
50/33
1.0mA/20mA
TC
U
Terminal count up (carry) output (active Low)
50/33
1.0mA/20mA
TC
D
Terminal count down (borrow) output (active Low)
50/33
1.0mA/20mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20
A in the High state and 0.6mA in the Low state.
Philips Semiconductors
Product specification
74F193
Up/down binary counter with separate up/down clocks
1995 Jul 17
5
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
0.5 to +7.0
V
V
IN
Input voltage
0.5 to +7.0
V
I
IN
Input current
30 to +5.0
mA
V
OUT
Voltage applied to output in High output state
0.5 to +V
CC
V
I
OUT
Current applied to output in Low output state
40
mA
T
amb
Operating free-air temperature range
0 to +70
C
T
stg
Storage temperature
65 to +150
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
NOM
MAX
UNIT
V
CC
Supply voltage
4.5
5.0
5.5
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
I
IK
Input clamp current
18
mA
I
OH
High-level output current
1
mA
I
OL
Low-level output current
20
mA
T
amb
Operating free-air temperature range
0
+70
C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
NO TAG
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
NO TAG
MIN
TYP
NO TAG
MAX
UNIT
V
O
High level output voltage
V
CC
=
MIN, V
IL
=
MAX,
"
10%V
CC
2.5
V
V
OH
High-level output voltage
V
CC
=
MIN, V
IL
=
MAX,
I
OH
= MAX, V
IH
= MIN
"
5%V
CC
2.7
3.4
V
V
O
Low level output voltage
V
CC
=
MIN, V
IL
=
MAX,
"
10%V
CC
0.35
0.50
V
V
OL
Low-level output voltage
V
CC
=
MIN, V
IL
=
MAX,
I
OL
= MAX, V
IH
= MIN
"
5%V
CC
0.35
0.50
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
0.73
1.2
V
I
I
Input current at maximum
input voltage
V
CC
= MAX, V
I
= 7.0V
100
A
I
IH
High-level input current
V
CC
= MAX, V
I
= 2.7V
20
A
I
IL
Low-level input
CP
U
, CP
D
V
CC
= MAX V = 0 5V
1.8
mA
Low level in ut
current
Others
V
CC
= MAX, V
I
= 0.5V
0.6
mA
I
OS
Short-circuit output current
NO TAG
V
CC
= MAX
60
150
mA
I
CC
Supply current (total)
4
V
CC
= MAX
32
50
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
4. Measure I
CC
with parallel load and Master reset inputs grounded, all other inputs at 4.5V and all outputs open.
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