1.
General description
The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible with low power
Schottky TTL (LSTTL). The 74HC137 is specified in compliance with JEDEC
standard no. 7A.
The 74HC137 is a 3-to-8 line decoder, demultiplexer with latches at the three address
inputs (An). The 74HC137 essentially combines the 3-to-8 decoder function with a 3-bit
storage latch. When the latch is enabled (LE = LOW), the 74HC137 acts as a 3-to-8 active
LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present
at the inputs before this transition, is stored in the latches. Further address changes are
ignored as long as LE remains HIGH.
The output enable input (E1 and E2) controls the state of the outputs independent of the
address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH.
The 74HC137 is ideally suited for implementing non-overlapping decoders in 3-state
systems and strobed (stored address) applications in bus oriented systems.
2.
Features
s
Combines 3-to-8 decoder with 3-bit latch
s
Multiple input enable for easy expansion or independent controls
s
Active LOW mutually exclusive outputs
s
Low-power dissipation
s
Complies with JEDEC standard no. 7A
s
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
Multiple package options
s
Specified from
-
40
C to +80
C and from
-
40
C to +125
C.
74HC137
3-to-8 line decoder, demultiplexer with address latches;
inverting
Rev. 03 -- 11 November 2004
Product data sheet
9397 750 13804
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 -- 11 November 2004
2 of 19
Philips Semiconductors
74HC137
3-to-8 line decoder, demultiplexer with address latches; inverting
3.
Quick reference data
[1]
C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
N +
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
4.
Ordering information
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t
PHL
, t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
An to Yn
-
18
-
ns
LE to Yn
-
17
-
ns
E1 to Yn
-
15
-
ns
E2 to Yn
-
15
-
ns
C
I
input capacitance
-
3.5
-
pF
C
PD
power dissipation
capacitance
V
I
= GND to V
CC
[1]
-
57
-
pF
Table 2:
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74HC137N
-
40
C to +125
C
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
74HC137D
-
40
C to +125
C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HC137DB
-
40
C to +125
C
SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
9397 750 13804
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 -- 11 November 2004
3 of 19
Philips Semiconductors
74HC137
3-to-8 line decoder, demultiplexer with address latches; inverting
5.
Functional diagram
Fig 1.
Functional diagram
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
001aab881
Y0
Y1
Y2
3 TO 8
DECODER
INPUT
LATCHES
Y3
Y4
Y5
Y6
Y7 7
9
10
11
12
13
14
15
A0
A1
E1
E2
A2
LE
4
3
5
6
2
1
001aab879
Y0
Y1
Y2
3 TO 8
DECODER
INPUT
LATCHES
Y3
Y4
Y5
Y6
Y7
7
9
10
11
12
13
14
15
A0
A1
E1
E2
5
6
A2
LE
4
3
2
1
001aab880
0
1
2
3
4
5
6
7
7
9
10
11
12
13
14
15
C8
8D,1
8D,2
X/Y
EN
&
2
8D,4
3
5
6
1
4
0
1
2
3
4
5
6
7
7
9
10
11
12
13
14
15
C8
0
8D,G
0
7
DX
&
2
2
3
5
6
1
4
9397 750 13804
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 -- 11 November 2004
4 of 19
Philips Semiconductors
74HC137
3-to-8 line decoder, demultiplexer with address latches; inverting
6.
Pinning information
6.1 Pinning
Fig 4.
Logic diagram
001aab882
E1
E2
A0
A1
A2
LE
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
A0
A0
LE
LE
LATCH
A1
A1
LE
LE
LATCH
A2
A2
LE
LE
LATCH
Fig 5.
Pin configuration
137
A0
V
CC
A1
Y0
A2
Y1
LE
Y2
E1
Y3
E2
Y4
Y7
Y5
GND
Y6
001aab878
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
9397 750 13804
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 -- 11 November 2004
5 of 19
Philips Semiconductors
74HC137
3-to-8 line decoder, demultiplexer with address latches; inverting
6.2 Pin description
7.
Functional description
7.1 Function table
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don't care.
Table 3:
Pin description
Symbol
Pin
Description
A0
1
data input 0
A1
2
data input 1
A2
3
data input 2
LE
4
latch enable input (active LOW)
E1
5
data enable input 1 (active LOW)
E2
6
data enable input 2 (active HIGH)
Y7
7
multiplexer output 7
GND
8
ground (0 V)
Y6
9
multiplexer output 6
Y5
10
multiplexer output 5
Y4
11
multiplexer output 4
Y3
12
multiplexer output 3
Y2
13
multiplexer output 2
Y1
14
multiplexer output 1
Y0
15
multiplexer output 0
V
CC
16
positive supply voltage
Table 4:
Function table
[1]
Enable
Input
Output
LE
E1
E2
A0
A1
A2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
H
L
H
X
X
X
stable
X
H
X
X
X
X
H
H
H
H
H
H
H
H
X
X
L
X
X
X
H
H
H
H
H
H
H
H
L
L
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
L
H
L
H
H
L
H
H
H
H
H
H
H
L
H
H
H
L
H
H
H
H
L
L
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
PDF 
ZIP