Document Outline
- FEATURES
- GENERAL DESCRIPTION
- QUICK REFERENCE DATA
- ORDERING INFORMATION
- PIN DESCRIPTION
- APPLICATIONS
- FUNCTION TABLE
- DC CHARACTERISTICS
- AC CHARACTERISTICS
- AC WAVEFORMS
- PACKAGE OUTLINES
DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT164
8-bit serial-in/parallel-out shift
register
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74HC/HCT164
FEATURES
Gated serial data inputs
Asynchronous master reset
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT164 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT164 are 8-bit edge-triggered shift registers
with serial data entry and an output from each of the eight
stages.
Data is entered serially through one of two inputs (D
sa
or
D
sb
); either input can be used as an active HIGH enable for
data entry through the other input.
Both inputs must be connected together or an unused
input must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH
transition of the clock (CP) input and enters into Q
0
, which
is the logical AND of the two data inputs (D
sa
,D
sb
) that
existed one set-up time prior to the rising clock edge.
A LOW level on the master reset (MR) input overrides all
other inputs and clears the register asynchronously,
forcing all outputs LOW.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
CP to Q
n
MR to Q
n
C
L
= 15 pF; V
CC
= 5 V
12
11
14
16
ns
ns
f
max
maximum clock frequency
78
61
MHz
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per
package
notes 1 and 2
40
40
pF
December 1990
3
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74HC/HCT164
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 2
D
sa
, D
sb
data inputs
3, 4, 5, 6, 10, 11, 12, 13
Q
0
to Q
7
outputs
7
GND
ground (0 V)
8
CP
clock input (LOW-to-HIGH, edge-triggered)
9
MR
master reset input (active LOW)
14
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74HC/HCT164
APPLICATIONS
Serial data transfer
FUNCTION TABLE
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced input one set-up time prior to the
LOW-to-HIGH clock transition
= LOW-to-HIGH clock transition
OPERATING MODES
INPUTS
OUTPUTS
MR
CP
D
sa
D
sb
Q
0
Q
1
-
Q
7
reset (clear)
L
X
X
X
L
L
-
L
shift
H
H
H
H
l
l
h
h
l
h
l
h
L
L
L
H
q
0
-
q
6
q
0
-
q
6
q
0
-
q
6
q
0
-
q
6
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74HC/HCT164
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min.
typ.
max.
min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
41
15
12
170
34
29
215
43
37
255
51
43
ns
2.0
4.5
6.0
Fig.6
t
PHL
propagation delay
MR to Q
n
39
14
11
140
28
24
175
35
30
210
42
36
ns
2.0
4.5
6.0
Fig.6
t
THL
/ t
TLH
output transition
time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.6
t
W
clock pulse width
HIGH or LOW
80
16
14
14
5
4
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
t
W
master reset pulse
width; LOW
60
12
10
17
6
5
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.6
t
rem
removal time
MR to CP
60
12
10
17
6
5
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.6
t
su
set-up time
D
sa
, D
sb
to CP
60
12
10
8
3
2
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.6
t
h
hold time
D
sa
, D
sb
to CP
4
4
4
-
6
-
2
-
2
4
4
4
4
4
4
ns
2.0
4.5
6.0
Fig.6
f
max
maximum clock
pulse frequency
6
30
35
23
71
85
5
24
28
4
20
24
MHz
2.0
4.5
6.0
Fig.6
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