Document Outline
- FEATURES
- GENERAL DESCRIPTION
- QUICK REFERENCE DATA
- ORDERING INFORMATION
- PIN DESCRIPTION
- APPLICATIONS
- FUNCTION TABLE
- RATINGS
- DC CHARACTERISTICS FOR 74HC
- AC CHARACTERISTICS FOR 74HC
- DC CHARACTERISTICS FOR 74HCT
- AC CHARACTERISTICS FOR 74HCT
- APPLICATION DIAGRAMS
- AC WAVEFORMS
- PACKAGE OUTLINES
DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT4543
BCD to 7-segment
latch/decoder/driver for LCDs
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver
for LCDs
74HC/HCT4543
FEATURES
Latch storage of BCD inputs
Blanking inputs
Output capability: non-standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4543 are high-speed Si-gate CMOS
devices and are pin compatible with "4543" of the "4000B"
series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4543 are BCD to 7-segment
latch/decoder/drivers for liquid crystal displays. They have
four address inputs (D
0
to D
3
), an active HIGH latch
disable input (LD), an active HIGH blanking input (BI), an
active HIGH phase input (PH) and seven buffered
segment outputs (Q
a
to Q
g
).
The "4543" provides the function of a 4-bit storage latch
and an 8-4-2-1 BCD to 7-segment decoder driver. The
"4543" can invert the logic levels of the output combination.
The phase (PH), blanking (BI) and latch disable (LD)
inputs are used to reverse the function table phase, blank
the display and store a BCD code, respectively.
For liquid crystal displays a square-wave is applied to PH
and the electrical common back-plane of the display. The
outputs of the "4543" are directly connected to the
segments of the liquid crystal.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
D
n
to Q
n
29
33
ns
LD to Q
n
32
31
ns
BI to Q
n
20
28
ns
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per package
notes 1 and 2
42
42
pF
December 1990
3
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver for
LCDs
74HC/HCT4543
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
LD
latch disable input (active HIGH)
5, 3, 2, 4
D
0
to D
3
address (data) inputs
6
PH
phase input (active HIGH)
7
BI
blanking input (active HIGH)
8
GND
ground (0 V)
9, 10, 11, 12, 13, 15, 14
Q
a
to Q
g
segment outputs
16
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver for
LCDs
74HC/HCT4543
Fig.4 Functional diagram.
Fig.5 Segment designation.
APPLICATIONS
Driving LCD displays
Driving fluorescent displays
Driving incandescent displays
Driving gas discharge displays
FUNCTION TABLE
Notes
1. For liquid crystal displays, apply a square-wave to PH.
2. Depends upon the BCD-code previously applied when LD = HIGH.
H = HIGH voltage level
L = LOW voltage level
X = don't care
INPUTS
OUTPUTS
DISPLAY
LD
BI
PH
(1)
D
3
D
2
D
1
D
0
Q
a
Q
b
Q
c
Q
d
Q
e
Q
f
Q
g
X
H
L
X
X
X
X
L
L
L
L
L
L
L
blank
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
L
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
L
H
L
H
L
L
L
L
L
H
H
0
1
2
3
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
L
H
H
H
H
L
L
H
H
H
H
H
L
H
H
L
L
L
H
L
H
H
H
L
H
H
H
L
4
5
6
7
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
L
L
L
H
H
L
L
H
H
L
L
8
9
blank
blank
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
blank
blank
blank
blank
L
L
L
X
X
X
X
(1)
(1)
as
above
H
as above
inverse of above
as
above
December 1990
5
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver for
LCDs
74HC/HCT4543
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134).
For RATINGS see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
, standard outputs.
Fig.6 Logic diagram.
Fig.7 Display.
December 1990
6
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver for
LCDs
74HC/HCT4543
DC CHARACTERISTICS FOR 74HC
Output capability: non-standard
I
CC
category: MSI
Voltages are referenced to GND (ground = 0 V)
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
V
I
OTHER
+
25
-
40 to
+
85
-
40 to
+
125
min.
typ.
max.
min.
max.
min.
max.
V
IH
HIGH level input
voltage
1.5
3.15
4.2
1.2
2.4
3.1
1.5
3.15
4.2
1.5
3.15
4.2
V
2.0
4.5
6.0
V
IL
LOW level input
voltage
0.7
1.8
2.8
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
2.0
4.5
6.0
V
OH
HIGH level
output voltage
1.9
4.4
5.9
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
V
2.0
4.5
6.0
V
IH
or
V
IL
-
I
O
= 20
A
-
I
O
= 20
A
-
I
O
= 20
A
V
OH
HIGH level
output voltage
3.98
5.48
0.15
0.16
3.84
5.34
3.7
5.2
V
4.5
6.0
V
IH
or
V
IL
-
I
O
= 1.0 mA
-
I
O
= 1.3 mA
V
OL
LOW level
output voltage
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
2.0
4.5
6.0
V
IH
or
V
IL
I
O
= 20
A
I
O
= 20
A
I
O
= 20
A
V
OL
LOW level
output voltage
0.15
0.16
0.26
0.26
0.33
0.33
0.4
0.4
V
4.5
6.0
V
IH
or
V
IL
I
O
= 1.0 mA
I
O
= 1.3 mA
I
I
input leakage
current
0.1
1.0
1.0
A
6.0
V
CC
or
GND
I
CC
quiescent
supply current
8.0
80.0
160.0
A
6.0
V
CC
or
GND
I
O
= 0
December 1990
7
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver for
LCDs
74HC/HCT4543
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
OTHER
+
25
-
40 to
+
85
-
40 to
+
125
min.
typ.
max. min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
D
n
to Q
n
91
33
26
340
68
58
425
85
72
510
102
87
ns
2.0
4.5
6.0
Fig.12
t
PHL
/ t
PLH
propagation delay
LD to Q
n
102
37
30
370
74
63
465
93
79
555
111
94
ns
2.0
4.5
6.0
Fig.13
t
PHL
/ t
PLH
propagation delay
BI to Q
n
66
24
19
265
53
45
330
66
56
400
80
68
ns
2.0
4.5
6.0
Fig.14
t
PHL
/ t
PLH
propagation delay
PH to Q
n
55
20
16
200
40
34
250
50
43
300
60
51
ns
2.0
4.5
6.0
t
THL
/ t
TLH
output transition time
63
23
18
250
50
43
315
63
54
375
75
64
ns
2.0
4.5
6.0
Figs 12, 13 and 14
t
W
LD pulse width
HIGH or LOW
35
7
6
11
4
3
45
9
8
55
11
9
ns
2.0
4.5
6.0
Fig.13
t
su
set-up time
D
n
to LD
60
12
10
8
3
2
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.15
t
h
hold time
D
n
to LD
30
6
5
3
1
1
40
8
7
45
9
8
ns
2.0
4.5
6.0
Fig.15
December 1990
8
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver for
LCDs
74HC/HCT4543
DC CHARACTERISTICS FOR 74HCT
Output capability: non-standard
I
CC
category: MSI
Voltages are referenced to GND (ground = 0 V)
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
V
I
OTHER
+
25
-
40 to
+
85
-
40 to
+
125
min.
typ.
max. min. max. min.
max.
V
IH
HIGH level input
voltage
2.0
1.6
2.0
2.0
V
4.5
to
5.5
V
IL
LOW level input
voltage
1.2
0.8
0.8
0.8
V
4.5
to
5.5
V
OH
HIGH level output
voltage
4.4
4.5
4.4
4.4
V
4.5
V
IH
or
V
IL
-
I
O
= 20
A
V
OH
HIGH level output
voltage
3.98
4.32
3.84
3.7
V
4.5
V
IH
or
V
IL
-
I
O
= 1.0 mA
V
OL
LOW level output
voltage
0
0.1
0.1
0.1
V
4.5
V
IH
or
V
IL
I
O
= 20
A
V
OL
LOW level output
voltage
0.15
0.26
0.33
0.4
V
4.5
V
IH
or
V
IL
I
O
= 1.0 mA
I
I
input leakage
current
0.1
1.0
1.0
A
5.5
V
CC
or
GND
I
CC
quiescent supply
current
8.0
80.0
160.0
A
5.5
V
CC
or
GND
I
O
= 0
I
CC
additional
quiescent supply
current per input
pin for unit load
coefficient is 1
(note 1)
100
360
450
490
A
4.5
to
5.5
V
CC
-
2.1V
other inputs
at V
CC
or
GND; I
O
= 0
December 1990
9
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver for
LCDs
74HC/HCT4543
Note to HCT types
The value of additional quiescent supply current (
I
CC
) for a unit load of 1 is given here.
To determine
I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
INPUT
UNIT LOAD COEFFICIENT
D
0
, D
1
, D
2
D
3
BI
LD
PH
1.00
0.50
0.50
1.50
1.25
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
OTHER
+
25
-
40 to
+
85
-
40 to
+
125
min.
typ.
max. min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
D
n
to Q
n
38
80
100
120
ns
4.5
Fig.12
t
PHL
/ t
PLH
propagation delay
LD to Q
n
36
68
85
102
ns
4.5
Fig.13
t
PHL
/ t
PLH
propagation delay
BI to Q
n
32
66
83
99
ns
4.5
Fig.14
t
PHL
/ t
PLH
propagation delay
PH to Q
n
24
66
83
99
ns
4.5
t
THL
/ t
TLH
output transition time
23
50
63
75
ns
4.5
Figs 12, 13 and 14
t
W
LD pulse width
HIGH or LOW
10
4
13
15
ns
4.5
Fig.13
t
su
set-up time
D
n
to LD
12
4
15
18
ns
4.5
Fig.15
t
h
hold time
D
n
to LD
8
2
10
12
ns
4.5
Fig.15
December 1990
10
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver for
LCDs
74HC/HCT4543
APPLICATION DIAGRAMS
Fig.8
Connection to liquid crystal (LCD) display
readout.
Fig.9
Connection to incandescent display
readout.
Fig.10 Connection to gas discharge display
readout.
Fig.11 Connection to fluorescent display readout.
December 1990
11
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver for
LCDs
74HC/HCT4543
AC WAVEFORMS
Fig.12 Waveforms showing the address input (D
n
)
to output (Q
n
) propagation delays and the
output transition times.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.13 Waveforms showing the latch disable input
(LD) to output (Q
n
) propagation delays and
the output transition times.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.14 Waveforms showing the blanking (BI) to
output (Q
n
) propagation delays and the
output transition times.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
PACKAGE OUTLINES
See
"74HC/HCT/HCU/HCMOS Logic Package Outlines"
.
Fig.15 Waveforms showing the address (D
n
) to
latch disable (LD) input set-up and hold
times.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
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